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CMOS Fabrication Process Overview

The document outlines the key steps in the CMOS process for fabricating integrated circuits including n-well diffusion, thin oxide growth, guarding implantations, LOCOS isolation, gate oxide growth, source and drain formations, contact etching, and metal deposition for interconnections. It also briefly discusses twin-well CMOS, BiCMOS, and dielectric isolation processes.

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Roshdy AbdelRassoul
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4 views10 pages

CMOS Fabrication Process Overview

The document outlines the key steps in the CMOS process for fabricating integrated circuits including n-well diffusion, thin oxide growth, guarding implantations, LOCOS isolation, gate oxide growth, source and drain formations, contact etching, and metal deposition for interconnections. It also briefly discusses twin-well CMOS, BiCMOS, and dielectric isolation processes.

Uploaded by

Roshdy AbdelRassoul
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd

CMOS

EE 7240 Integrated Circuit Engineering, Dr. J.B. Lee

Source: [Link]

CMOS process (1)


N-well diffusion

Thin oxide growth

Si3N4 as a barrier

EE 7240 Integrated Circuit Engineering, Dr. J.B. Lee

Source: [Link]

CMOS process (2)


N+ guarding implantation

P+ guarding implantation

Thick oxide junction isolation


LOCOS
(Local oxidation of silicon)
EE 7240 Integrated Circuit Engineering, Dr. J.B. Lee

Source: [Link]

CMOS process (3)


Si3N4 barrier and
thin oxide strip

Growth of gate oxide

Poly-I as a gate electrode

EE 7240 Integrated Circuit Engineering, Dr. J.B. Lee

Source: [Link]

CMOS process (4)


Formation of p-channel
drain and source

Formation of n-channel
drain and source

Growth of SiO2

EE 7240 Integrated Circuit Engineering, Dr. J.B. Lee

Source: [Link]

CMOS process (5)


Etching of SiO2 for contacts

Deposit metal and


selective etching for
interconnection

EE 7240 Integrated Circuit Engineering, Dr. J.B. Lee

Source: [Link]

Twin-well CMOS (1)

TiN barrier

W-plug
Salicide

EE 7240 Integrated Circuit Engineering, Dr. J.B. Lee

CMP

Twin-well CMOS (2)

Global interconnection

EE 7240 Integrated Circuit Engineering, Dr. J.B. Lee

BiCMOS

EE 7240 Integrated Circuit Engineering, Dr. J.B. Lee

Dielectric isolation

EE 7240 Integrated Circuit Engineering, Dr. J.B. Lee

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