Appendix- 4A
VERILOG CODE OF SHIFT-ADD MULTIPLIER
`define width 16
`timescale 1ns/1ps
module shift_add (p, x, y);
parameter width=`width;
input[width-1:0]x, y;
output[width-1:0]p;
reg [width:0] pp[width-1:0];
reg [width-1:0] spp[width-1:0];
reg [width-1:0] prod;
integer kk,ii;
always @ (x or y)
begin
for(kk=0;kk<width;kk=kk)
begin
case(x[kk])
1'b0 : pp[kk]= 0;
1'b1 : pp[kk]= y;
default : pp[kk] = 0;
endcase
spp[kk] = $signed(pp[kk]);
for(ii=0;ii<kk;ii=ii)
spp[kk] = {spp[kk],1'b0};
end
prod = spp[0];
for(kk=1;kk<width;kk=kk)
prod = prod spp[kk];
end
assign p = prod;
endmodule
39
Appendix- 4B
VERILOG CODE OF BOOTH MULTILPIER
`define width 16
`timescale 1ns/1ps
module booth_mult (p, x, y);
parameter width=`width;
parameter N = `width/2;
input[width-1:0]x, y;
output[width+width-1:0]p;
reg [2:0] cc[N-1:0];
reg [width:0] pp[N-1:0];
reg [width+width-1:0] spp[N-1:0];
reg [width+width-1:0] prod;
wire [width:0] inv_x;
integer kk,ii;
assign inv_x = {~x[width-1],~x}+1;
always @ (x or y or inv_x)
begin
cc[0] = {y[1],y[0],1'b0};
for(kk=1;kk<N;kk=kk+1)
cc[kk] = {y[2*kk+1],y[2*kk],y[2*kk-1]};
for(kk=0;kk<N;kk=kk+1)
begin
case(cc[kk])
3'b001 , 3'b010 : pp[kk] = {x[width-1],x};
3'b011 : pp[kk] = {x,1'b0};
3'b100 : pp[kk] = {inv_x[width-1:0],1'b0};
3'b101 , 3'b110 : pp[kk] = inv_x;
default : pp[kk] = 0;
endcase
spp[kk] = $signed(pp[kk]);
for(ii=0;ii<kk;ii=ii+1)
spp[kk] = {spp[kk],2'b00};
end
prod = spp[0];
for(kk=1;kk<N;kk=kk+1)
prod = prod + spp[kk];
end
assign p = prod;
endmodule
40
Appendix-4C
VERILOG CODE OF VEDIC MULTIPLIER
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////
////////////
// Company:
// Engineer:
//
// Create Date:
16:06:33 04/20/2014
// Design Name:
// Module Name:
vedic_16x16
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////
////////////
module vedic_16x16(a,b,c
);
input [15:0]a;
input [15:0]b;
output [31:0]c;
wire
wire
wire
wire
wire
wire
wire
wire
wire
wire
wire
wire
[15:0]q0;
[15:0]q1;
[15:0]q2;
[15:0]q3;
[31:0]c;
[15:0]temp1;
[23:0]temp2;
[23:0]temp3;
[23:0]temp4;
[15:0]q4;
[23:0]q5;
[23:0]q6;
vedic_8X8
vedic_8X8
vedic_8X8
vedic_8X8
z1(a[7:0],b[7:0],q0[15:0]);
z2(a[15:8],b[7:0],q1[15:0]);
z3(a[7:0],b[15:8],q2[15:0]);
z4(a[15:8],b[15:8],q3[15:0]);
41
assign temp1 ={8'b0,q0[15:8]};
add_16_bit z5(q1[15:0],temp1,q4);
assign temp2 ={8'b0,q2[15:0]};
assign temp3 ={q3[15:0],8'b0};
add_24_bit z6(temp2,temp3,q5);
assign temp4={8'b0,q4[15:0]};
add_24_bit z7(temp4,q5,q6);
assign c[7:0]=q0[7:0];
assign c[31:8]=q6[23:0];
endmodule
module ps2_rx
(
input wire clk, reset,
input wire ps2d, ps2c, rx_en,
output reg rx_done_tick,
output wire [3:0] data_out1/*,
output reg [4:0] count2*/
);
// s y m b o l i c s t a t e d e c l a r a t i o n
localparam [1:0]
idle = 2 'b00,
dps = 2'b01,
load = 2'b10;
// s i g n u l d e c l a r a t i o n
reg [1:0] state_reg , state_next ;
reg [7:0] filter_reg;
wire [7:0] filter_next ;
reg f_ps2c_reg ;
wire f_ps2c_next ;
reg [3:0] n_reg , n_next ;
reg [10:0] b_reg, b_next;
wire fall_edge ;
//reg [1:0] flag=2'b0;
// f i l t e r and f a l l i n g - e d g e t i c k g e n e r a t i o n
f o r ps2c
always@( posedge clk , posedge reset )
if(reset)
begin
filter_reg <= 0 ;
f_ps2c_reg <= 0;
end
else
42
begin
filter_reg <= filter_next ;
f_ps2c_reg <= f_ps2c_next ;
end
assign filter_next= {ps2c, filter_reg[7:1]};
assign f_ps2c_next= {filter_reg==8'b11111111} ? 1'b1
:(filter_reg==8'b00000000) ? 1'b0 :f_ps2c_reg;
assign fall_edge = f_ps2c_reg &(~f_ps2c_next);
// FSMD s t a t e & d a t a r e g i s t e r s
always@( posedge clk , posedge reset )
if(reset)
begin
state_reg <= idle;
n_reg <= 0;
b_reg <= 0;
//flag<=2'b0;
end
else
begin
state_reg <= state_next ;
n_reg <= n_next;
b_reg <= b_next;
end
// FSMD n e x t - s t a t e l o g i c
always@(*)
begin
state_next = state_reg;
rx_done_tick = 1'b0;
n_next = n_reg;
b_next = b_reg;
case(state_reg)
idle :
if(fall_edge & rx_en)
begin
// s h i f t in s t a r t b i t
b_next = {ps2d, b_reg[10:1]};
n_next = 4'b1001;
state_next = dps;
end
dps: // 8 datu + I p a r i t y + I s t o p
if(fall_edge)
begin
b_next = {ps2d, b_reg[10:1]};
if(n_reg==0)
begin
state_next = load;
/*if(flag==2'b11)
flag<=2'b0;
else
43
flag<=flag+1;*/
end
else
n_next = n_reg-4'b0001 ;
end
load: // I e x t r a c l o c k t o c o m p l e t e the l a s t s h i
f t
begin
state_next = idle ;
rx_done_tick = 1'b1;
end
endcase
end
assign data_out1 = (b_reg[8:1]==8'h45)?4'b0000:
(b_reg[8:1]==8'h16)?4'b0001:
(b_reg[8:1]==8'h1e)?4'b0010:
(b_reg[8:1]==8'h26)?4'b0011:
(b_reg[8:1]==8'h25)?4'b0100:
(b_reg[8:1]==8'h2e)?4'b0101:
(b_reg[8:1]==8'h36)?4'b0110:
(b_reg[8:1]==8'h3d)?4'b0111:
(b_reg[8:1]==8'h3e)?4'b1000:
(b_reg[8:1]==8'h46)?4'b1001:
(b_reg[8:1]==8'h1c)?4'b1010:
(b_reg[8:1]==8'h32)?4'b1011:
(b_reg[8:1]==8'h21)?4'b1100:
(b_reg[8:1]==8'h23)?4'b1101:
(b_reg[8:1]==8'h24)?4'b1110:
(b_reg[8:1]==8'h2b)?4'b1111:4'b0000;
a bits
endmodule
module mem(input [3:0] data_out1,
output reg [15:0] in1,in2,
input clk,clk2,reset,
output reg [2:0] count
);
always@(negedge clk2 or negedge reset)
begin
if(~reset)
count<=3'b0;
else
count<=count+3'b001;
end
always@(posedge clk)
begin
case(count)
44
// d a t
3'd0: in1[15:12]<=data_out1;
3'd1: in1[11:8]<=data_out1;
3'd2: in1[7:4]<=data_out1;
3'd3: in1[3:0]<=data_out1;
3'd4: in2[15:12]<=data_out1;
3'd5: in2[11:8]<=data_out1;
3'd6: in2[7:4]<=data_out1;
3'd7: in2[3:0]<=data_out1;
endcase
end
endmodule
module final_mult(input wire clk, reset,clk2,
input wire ps2d, ps2c, rx_en,
output reg sf_e,e,rs,r_w,d,c,b,a,
output wire [2:0] count
);
wire rx_done_tick;
wire [3:0] data_out1;
wire [15:0] in1,in2;
wire [31:0] prod;
wire [7:0] temp[0:15];
reg [26:0] lcd_count;
reg [5:0]code;
reg refresh;
ps2_rx d1( clk, reset,ps2d, ps2c, rx_en,rx_done_tick,data_out1);
mem m1(data_out1,in1,in2,clk,clk2,reset,count);
vedic_16x16 v1(in1,in2,prod);
hex_ascii
a1(in1[3:0],temp[0][7:0]),a2(in1[7:4],temp[1][7:0]),a3(in1[11:8],temp[
2][7:0]),a4(in1[15:12],temp[3][7:0]),
a5(in2[3:0],temp[4][7:0]),a6(in2[7:4],temp[5][7:0]),a7(in2[11:8],temp[
6][7:0]),a8(in2[15:12],temp[7][7:0]),
a9(prod[3:0],temp[8][7:0]),a10(prod[7:4],temp[9][7:0]),a11(prod[1
1:8],temp[10][7:0]),a12(prod[15:12],temp[11][7:0]),
a13(prod[19:16],temp[12][7:0]),a14(prod[23:20],temp[13][7:0]),a15(prod
[27:24],temp[14][7:0]),a16(prod[31:28],temp[15][7:0]);
always @(posedge clk ) begin
45
if(reset)
lcd_count<=0;
else
lcd_count <=lcd_count + 27'd1;
case ( lcd_count[26:21])
6'd0:code
6'd1:code
6'd2:code
6'd3:code
<=6'h03;
<=6'h03;
<=6'h03;
<=6'h02;
///initializing the lcd
6'd4:code <=6'h02;
6'd5:code <=6'h08;
///function mode
6'd6:code <=6'h00;
6'd7:code <=6'h06;
//// entry mode set
6'd8:code <=6'h00;
6'd9:code <=6'h0C;
set
///disply on/off set command
6'd10:code <=6'h00;
6'd11:code <=6'h01; ///clear the lcd
6'd12:code <={2'b10, temp[3][7:4]};
6'd13:code <={2'b10, temp[3][3:0]};
///for character 'H'
6'd14:code <={2'b10, temp[2][7:4]};
6'd15:code <={2'b10, temp[2][3:0]};
///for character 'e'
6'd16:code <={2'b10, temp[1][7:4]};
6'd17:code <={2'b10,temp[1][3:0]};
///for character 'l'
6'd18:code <={2'b10, temp[0][7:4]};
6'd19:code <={2'b10,temp[0][3:0]}; ///for character 'l'
6'd20:code <={2'b10, 4'b0101};
6'd21:code <={2'b10,4'b1111};
///for character 'o'
6'd22:code <={2'b10, temp[7][7:4]};
6'd23:code <={2'b10,temp[7][3:0]};
///for character ','
6'd24:code <={2'b10, temp[6][7:4]};/*6'b001100;*/
6'd25:code <={2'b10,temp[6][3:0]};/*6'b000000;*/ ////set
DDRAM address for next line 0x40
6'd26:code <={2'b10, temp[5][7:4]};
6'd27:code <={2'b10,temp[5][3:0]}; ///command for "world
!"
6'd28:code <={2'b10, temp[4][7:4]};
46
6'd29:code <={2'b10,temp[4][3:0]};
6'd30:code <=6'b001100;
6'd31:code <=6'b000000;
6'd32:code <={2'b10, temp[15][7:4]};
6'd33:code <={2'b10,temp[15][3:0]};
6'd34:code <={2'b10, temp[14][7:4]};
6'd35:code <={2'b10,temp[14][3:0]};
6'd36:code <={2'b10, temp[13][7:4]};
6'd37:code <={2'b10,temp[13][3:0]};
6'd38:code <={2'b10, temp[12][7:4]};
6'd39:code <={2'b10,temp[12][3:0]};
6'd40:code <={2'b10, temp[11][7:4]};
6'd41:code <={2'b10, temp[11][3:0]};
6'd42:code <={2'b10, temp[10][7:4]};
6'd43:code <={2'b10, temp[10][3:0]};
6'd44:code <={2'b10, temp[9][7:4]};
6'd45:code <={2'b10, temp[9][3:0]};
6'd46:code <={2'b10, temp[8][7:4]};
6'd47:code <={2'b10, temp[8][3:0]};
default : code <=6'h10;
endcase
///busy flag
refresh <=lcd_count[20]; /// for enabling the lcd
sf_e <=1;
///pin "D16" of the fpga 1 for accessing
the lcd
{e,rs,r_w,d,c,b,a} <= {refresh,code};
end
endmodule
47
References:
[1] Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo Kim, Yong Beom Cho Multiplier
design based on ancient Indian Vedic Mathematics
in 2008 International SoC Design
Conference .
[2] H. Thapliyal, M. B. Srinivas and H. R. Arabnia , "Design And Analysis of a VLSI Based
High Performance Low Power Parallel square Architecture", in Proc. Int. Conf. Also. Math.
Compo. Sc., Las Vegas, June 2005, pp. 72-76
[3] Xilinx Spartan 3E User Guide.
[4] Harpreet Singh Dhillon and Abhijit Mitra "A Digital Multiplier Architecture using Urdhava
Tiryakbhyam Sutra of Vedic Mathematics" IEEE Conference Proceedings,2008.
[5] Hussin R An Efficient Modified Booth Multiplier Architecture published in Electronics
Design 2008 ICED.
48