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Standard Cell Library Design in VLSI

This document outlines the objectives, guidelines, tools, and design flow for developing a standard cell library. The objectives are to design a standard cell library to overcome restrictions of commercial libraries. The guidelines specify including common cells like AND, OR, NOT, flip flops. The tools used will be Cadence tools like Digital Implementation, Abstract Generator, and Design Compiler. The design flow involves schematic design, simulation, layout, extraction, and characterization to generate the standard cell library. Possible advancements discussed include controlling gate leakage, low voltage circuit implementation, and standby power reduction.

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Gagandeep Singh Dhingra
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85 views10 pages

Standard Cell Library Design in VLSI

This document outlines the objectives, guidelines, tools, and design flow for developing a standard cell library. The objectives are to design a standard cell library to overcome restrictions of commercial libraries. The guidelines specify including common cells like AND, OR, NOT, flip flops. The tools used will be Cadence tools like Digital Implementation, Abstract Generator, and Design Compiler. The design flow involves schematic design, simulation, layout, extraction, and characterization to generate the standard cell library. Possible advancements discussed include controlling gate leakage, low voltage circuit implementation, and standby power reduction.

Uploaded by

Gagandeep Singh Dhingra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Design & Development of

Standard Cell Library


Gagandeep Singh
Anurag
Siddhant Kukreti
[Link] (VLSI Design)
Objecties

T! Design Standard ce"" Librar#


$!%%ercia" "ibrar# ce""s are c!%pan#&s
pr!prietar# in'!r%ati!n( and understandab"#(
c!%panies usua""# i%p!se certain restricti!ns
!n the access and use !' their "ibrar# ce""s.
Th!se restricti!ns !n c!%%ercia" "ibrar# ce""s
seere"# ha%per VLSI research and teaching
actiities !' acade%ia
Guide"ines t! $reating a Standard $e""
Librar#

A standard ce"" "ibrar# %ust c!ntain at "east


the '!""!)ing ce""s t! be ab"e t! i%p"e%ent
an# 'uncti!n*
+ ,A,D
+ ,O-
+ ,OT
+ D ."ip ."!p etc
T!!"s /sed '!r $reating Standard $e""
Librar#

The '!""!)ing $AD T!!"s )i"" be used in


this tut!ria"*
+ $adence I$.0
+ $adence Abstract Generat!r
+ $adence Design 1"anner
+ 2S1I$3
Design ."!) .!r Standard $e"" Librar#
Speci'icati!ns
Design ,e)
Sche%atic
Meet
Spec 4
Generate
Si%u"ati!n $ircuit
Sche%atic
Se"ect
0est
Di%ensi!ns
Si%u"ati!n
Design ,e)
La#!ut
$e"" La#!ut
D-$5LVS

$haracteri6ati!
n
37tracti!n
Veri"!g
Generati!n
Abstract
Generati!n
S#%b!"
Generati!n
Standard $e""
Librar#
,!
8es
Virtu!s!
Sche%atic
3dit!r
Spectre
Virtu!s! La#!ut
3dit!r
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Librar#
$haracteri6ati!n
Abstract 3dit!r
.ig 9*+ Standard $e"" Librar# Design ."!)
Sche%atic
.ig :* + Sche%atic
.ig ;* + S#%b!" $reati!n
Si%u"ati!n <ae'!r%s = ,et"ist
.ig* + > Si%u"ati!n
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[Link]
.ig* + ? $ust!% La#!ut
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1!ssib"e adance%ents

$!ntr!" !' Gate Leakage '!r sub+9AAn% $MOS using


D!%in! L!gic.

Design !' "!) !"tage standard ce""s using techniBues


"ike s"eep# keeper.

Design !' Super bu''ers in sub+9AAn% $MOS


Techn!"!gies )ith Signi'icant Gate Leakage

L!) 1!)er VLSI $ircuit I%p"e%entati!n using Mi7ed


Static $MOS and D!%in! "!gic )ith De"a# 3"e%ents

Standb# p!)er reducti!n and S-AM ce"" !pti%i6ati!n '!r


sub 9AAn% techn!"!g#.

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