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CMOS Logic Gate Characteristics

This document contains 16 figures illustrating various digital logic circuits including NMOS pass transistor logic, inverters, NAND gates, NOR gates, XOR gates, buffers, D flip-flops, D latches, and setup time. Each figure shows the circuit diagram, inputs and outputs demonstrating the intended logic function. Transistor implementations of XOR and XNOR gates using the minimum number of transistors are also shown.

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Sumeet Saurav
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8 views9 pages

CMOS Logic Gate Characteristics

This document contains 16 figures illustrating various digital logic circuits including NMOS pass transistor logic, inverters, NAND gates, NOR gates, XOR gates, buffers, D flip-flops, D latches, and setup time. Each figure shows the circuit diagram, inputs and outputs demonstrating the intended logic function. Transistor implementations of XOR and XNOR gates using the minimum number of transistors are also shown.

Uploaded by

Sumeet Saurav
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

PracticalList

Figure1NMOSDCcharacteristic(Idv/sVdsatVgs=1v)..............................................................................2
Figure2:NMOSPassTransistorlogic.........................................................................................................2
Figure3:InverterDCCharacteristic............................................................................................................3
Figure4:InverterDCcharacteristicwithcalculationofVinv.....................................................................3
Figure5:Inverteroutput............................................................................................................................4
Figure6:TwoinputNANDgate..................................................................................................................4
Figure7:ThreeinputNANDgate................................................................................................................5
Figure8:Norgate.......................................................................................................................................5
Figure9:Xorgateusingcmos.....................................................................................................................6
Figure10:Xorusingtransmissiongate.......................................................................................................6
Figure11:Xorusing5transistors...............................................................................................................7
Figure12:Xnorusing4transistors.............................................................................................................7
Figure13:Bufferoutput.............................................................................................................................8
Figure14:DFlipFlopusingCMOS..............................................................................................................8
Figure15:DLatch.......................................................................................................................................9
Figure16:DFFSetuptime...........................................................................................................................9

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Figure1NMOSDCcharacteristic(Idv/sVdsatVgs=1v)

Figure2:NMOSPassTransistorlogic
[Link]
thatNMOScanpasslogiczeroeffectivelybutitpassesdegradedhighlogicthatiswith
thresholddrop.

2|P a g e

Figure3:InverterDCCharacteristic

Figure4:InverterDCcharacteristicwithcalculationofVinv
Vinvofinverteristhevoltagewheninputvoltageandoutputvoltageisequalsofrom
abovefigureitis1.266v.

3|P a g e

Figure5:Inverteroutput
Inabovefigureinputisa,andoutputisqwhichareinverseofeachother.

Figure6:TwoinputNANDgate
Inabovefigureinputisa,bandoutputisqwhichisshowingNANDrelationship(q=ab).
4|P a g e

Figure7:ThreeinputNANDgate
Inabovefigureinputisa,b,candoutputisqwhichisshowingNANDrelationship(q=
abc).

Figure8:Norgate
Inabovefigureinputisa,bandoutputisqwhichisshowingNORrelationship(q=a+b).

5|P a g e

Figure9:Xorgateusingcmos
Inabovefigureinputisa,bandoutputisqwhichisshowingXORrelationship(q=ab).

Figure10:Xorusingtransmissiongate
Inabovefigureinputisa,bandoutputisvoutwhichisshowingXORrelationship
(vout=ab).
6|P a g e

Figure11:Xorusing5transistors
Inabovefigureinputisa,bandoutputisvoutwhichisshowingXORrelationship
(vout= a b). This circuit is implemented by using minimum number of transistor (5
Transistor)anditisworkingperfectly.

Figure12:Xnorusing4transistors
Inabovefigureinputisa,bandoutputisvoutwhichisshowingXNORrelationship
7|P a g e

(vout =a b). This circuit is implemented by using minimum number of transistor (4


Transistor)anditisworkingperfectly,onlyathresholddropinoutputcomeswhenboth
inputsarehighasshownabove.

Figure13:Bufferoutput
Thisbufferisimplementedbyusingbacktobackinverter,whereoutputqisperfectly
replicaofinputa.

Figure14:DFlipFlopusingCMOS
Fromabovefigureitcanbeseenthatoutputqischangingitsvalueatrisingedgeof
clockpulseandqbarisjustoppositeofoutputq.
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Figure15:DLatch
[Link]
inputDonlyatthehighlevelofclockpulse.

Figure16:DFFSetuptime
Setuptimeisthetimebeforethearrivalofclockforwhichinputshouldbeatproper
[Link](50%)iscomingattime1.53nsandif
inputD(50%)iscomingafter1.43nsthenwewillgetlowoutputbuttogethighoutput
inputD(50%)shouldcomebeforeorat1.43ns.Sosetuptimeforabovecircuitis10ns.
9|P a g e

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