C++ engineer working on the RISC-V debug toolchain (OpenOCD, GDB, the Spike simulator) and on debug info for hardware designs.

I designed uhdi, a debug-info format for Chisel designs, and built it into CIRCT. firtool --emit-uhdi emits it, and the converters in the repo turn it into hgdb, HGLDD (Tywaves) and ChiselTrace PDG.

OpenOCD (riscv-openocd commits, openocd.org Gerrit): RISC-V memory access. One access path for reads and writes, an abstract-command cache, address-translation drivers, privilege and MPRV handling for program-buffer access, and hardware-translated virtual access through aamvirtual.

GDB (patches): analysing a RISC-V core file without the executable (ISA features from AT_HWCAP, FLEN from the NT_FPREGSET note size) and an arch= option for the RISC-V disassembler.

Spike (PRs): RISC-V Debug Spec. Abstract register and memory access that keeps hart state intact, mcontrol6 triggers, and fixes to Debug Mode entry and exit.