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Système Numérique : VHDL et Composants

Le document présente un système numérique composé d'un compteur, d'un codeur et d'un module combinatoire, avec des exercices sur la conception VHDL de ces composants. Les tâches incluent la création de tables de Karnaugh, la définition d'entités et l'écriture de programmes VHDL pour chaque module. Le système utilise des entrées de 3 bits et une horloge pour générer une sortie de 7 bits.

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7 vues4 pages

Système Numérique : VHDL et Composants

Le document présente un système numérique composé d'un compteur, d'un codeur et d'un module combinatoire, avec des exercices sur la conception VHDL de ces composants. Les tâches incluent la création de tables de Karnaugh, la définition d'entités et l'écriture de programmes VHDL pour chaque module. Le système utilise des entrées de 3 bits et une horloge pour générer une sortie de 7 bits.

Transféré par

kheddamyassine77
Copyright
© All Rights Reserved
Nous prenons très au sérieux les droits relatifs au contenu. Si vous pensez qu’il s’agit de votre contenu, signalez une atteinte au droit d’auteur ici.
Formats disponibles
Téléchargez aux formats PDF, TXT ou lisez en ligne sur Scribd

Ing.

GEIN TD3

Un système numérique est organisé selon Entree


E
l’architecture ci-contre autour d’un compteur, un Module1 S E1
Codeur Sortie
codeur et un module combinatoire. Le système S2
Horloge
dispose de trois entrées : « Entree » de 3bits, Clk S1 E2
« Horloge » et «Reset» de 1bit. La sortie « Sortie » Reset Compteur
Rst
est de 7bits.
Système Numérique

Exercice I E S
Le bloc « Module1 » est défini par la table de vérité ci-contre. E2 E1 E0 S2 S1 S0
3bits 3bits 0 0 0 0 1 1
E
Module1 S 0 0 1 1 1 1
0 1 0 1 1 0
1) Remplir les tableaux de Karnaugh pour simplifier les 0 1 1 0 1 1
équations de la sortie 1 0 0 0 0 1
E1E0 00 01 11 10 1 0 1 1 0 0
E2 1 1 0 1 0 1
0 1 1 1 0 1 1
1
E1E0 00 01 11 10
E1E0 00 01 11 10 E2
E2 0
0 1
1

2) Donner les équations de la sortie


3) Donner, en programmation VHDL, l’entité du bloc « Module1 ».
Library ieee ;
Use ieee.std_logic_1164.all ;

Entity Module1 is
Port ( _________________________________________________________________
_________________________________________________________________
_________________________________________________________________ );
______________________________________________________________________________

4) Compléter l’architecture du bloc « Module1 ».

Page 1 sur 4
Ing. GEIN TD3

Architecture Brancher of Module1 is


Begin
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________

Exercice II
1) Le bloc « Compteur » compte les valeurs impaires de 1 à 11 à chaque front montant de l’entrée
« Clk », c’est-à-dire la sortie S1 prend les valeurs 1-3-5-7-9-11-1-3-5…. Si l’entrée Rst=1
alors la sortie S1=1. Donner l’entité du bloc « Compteur ».
Library ieee ;
Use ieee.std_logic_1164.all ;
_______________________________________________________________________

Entity Compteur is
Port ( _________________________________________________________________
_________________________________________________________________
);
End Compteur;

2) compléter le programme VHDL pour réaliser le bloc « Compteur ».


Architecture Compter of Compteur is
Begin
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________

3) Le bloc « Codeur » permet d’afficher les valeurs fournies par le compteur sur un afficheur 7
segments. Ces valeurs arrivent en BCD sur l’entrée « E2 » de 4bits, et sortent (en 7 segments)
sur la sortie S2 de 7bits. L’entrée « E1 » de 3bits conditionne cet affichage. Donner l’entité
de ce bloc.

Page 2 sur 4
Ing. GEIN TD3

Library ieee ;
Use ieee.std_logic_1164.all ;

Entity Codeur is
Port ( _________________________________________________________________
_________________________________________________________________
_________________________________________________________________
);
End Codeur;

4) L’entrée « E1 » conditionne l’affichage selon la condition suivante : si E1>4 alors l’affichage


passe normalement, sinon on affiche 0 (S2=0) quelque-soit E2. Ecrire un programme VHDL
pour réaliser le bloc « Codeur ».
Architecture Coder of Codeur is
Begin
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________

Exercice III
1) Définir l’entité du système numérique complet.

Page 3 sur 4
Ing. GEIN TD3

Library ieee ;
Use ieee.std_logic_1164.all ;
Entity Systeme is
Port ( _________________________________________________________________
_________________________________________________________________
_________________________________________________________________
);
End Systeme;

2) En utilisant les blocs « Module1 », « Compteur » et « Codeur » sous forme de composants,


écrire un programme VHDL pour réaliser le système numérique complet.
Architecture Montage of Systeme is
Begin
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
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______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________

Page 4 sur 4

Common questions

Alimenté par l’IA

The digital system utilizes VHDL to define the entities and architectures of its key components: 'Module1', 'Compteur', and 'Codeur'. Each component's functionality is expressed through VHDL code, specifying ports and logical operations that achieve desired inputs and outputs. This includes entity declarations, architecture development, and potentially processes for sequential control, such as in the 'Compteur'. VHDL facilitates a clear, structured approach to implementing digital designs .

The key components of the digital system are 'Module1', 'Compteur', and 'Codeur'. 'Module1' processes 3-bit input to generate 7-bit output. The 'Compteur' is a counter for odd numbers between 1 and 11, resettable by 'Rst'. 'Codeur' converts BCD values from 'Compteur' for display on a 7-segment, conditioned by 'E1'. These components work together to manage input processing, counting, and display tasks, integrating several aspects of digital system design .

The condition 'E1 > 4' in the 'Codeur' block's display logic determines whether the values received from the 'Compteur' are shown on the 7-segment display. If 'E1' is greater than 4, then the associated input values are displayed correctly on 'S2'. If not, 'S2' outputs zero regardless of the actual value in 'E2'. This logic ensures that display outputs are selectively shown based on specific conditions, thus providing a controlled visual output mechanism .

In the digital system, the 'Reset' input, denoted as 'Rst', ensures the proper initialization and control of the 'Compteur'. When 'Rst' is asserted (set to 1), it forces the 'Compteur' output to reset to 1, thereby providing a known starting point for the counter operation regardless of prior states. This is crucial for predictable system behavior, preventing erroneous counting sequences and aiding in synchronization across the digital system .

The 'Codeur' block receives input values from the 'Compteur' in BCD format on its 4-bit input 'E2', and displays these on a 7-segment display via its 7-bit output 'S2'. The display behavior is conditioned by the 3-bit input 'E1'; if 'E1' is greater than 4, the values are displayed normally, otherwise 'S2' outputs 0 irrespective of 'E2' . The 'Codeur' thus serves as a display controller based on conditions determined by other system components.

The 'Compteur' block functions as a counter that cycles through odd numbers from 1 to 11, resuming from 1 after reaching 11. It counts on the rising edge of the 'Clk' input, resetting to 1 if 'Rst' is set to 1. The corresponding VHDL entity for this block must describe its functionality and complete its design in terms of ports and architecture .

Karnaugh maps are used for simplifying the output equations in digital circuits to minimize the number of logic gates required. By organizing the truth table into a 2D layout, patterns can be easily visualized, allowing for the grouping of adjacent entries that share common factors, thus enabling easy algebraic simplification. This process leads to more efficient digital designs in terms of complexity and performance .

To complete a VHDL program for the 'Compteur' block given its functionality, the program must define a process triggered on the rising edge of 'Clk'. Within this process, an internal signal (e.g., a register) keeps track of the count. If 'Rst' is high, the count resets to 1. Otherwise, the counter increments by 2 with checks to roll over from 11 back to 1. This logic can be encapsulated using an if-else conditional structure within the VHDL architecture .

The 'Module1' block in the digital system architecture processes a 3-bit input 'E' and generates a 7-bit output. It is defined by a truth table that the user needs to fill in a Karnaugh map for simplification of the output equations. Additionally, the entity for this block must be described using VHDL, where the architecture of 'Module1' is completed to meet the input-output specifications .

To combine the blocks 'Module1', 'Compteur', and 'Codeur' into a complete system, VHDL is used to instantiate each block as components within a top-level architecture, such as 'Montage' of 'Systeme'. The architecture coordinates the interaction between components by connecting their respective input and output signals. Signal mapping and correctly triggering each component form the core integration tasks, ensuring that data flows coherently from one block to the next as designed .

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