ModuleS_DSPAA Module Interfacing Memory and Parallel 1/O Peripherals to Programmable DSP Devices: Introduction, Memory Space Organization, External Bus Interfacing Signals. Memory Interface, Parallel V/O Interface, Programmed I/O, Interrupts and I/O Direct Memory Access (DMA). Interfacing and Applications of DSP Processors: Introduction, Synchronous Serial Interface, A CODEC Interface Circuit, DSP Based Bio- telemetry Receiver, A Speech Processing System, An Image Processing System. L1, L2, L3 Unit 1: Interfacing Memory & Parallel I/O Peripherals to DSP Devices 5.1 Introduction: * Atypical DSP system has DSP with extemal memory, input devices and output devices. * Since the manufacturers of memory and VO devices are not-same-as that of manufacturers of DSP and also since there are variety of memory and 1/0 devices available, the signals generated by DSP may not suit memory and /O devices to be connected to DSP. ‘+ Thus, there is a need for interfacing devices the purpose of it being to use DSP signals to generate the appropriate signals for setting up communication with the memory. © DSP with interface is shown in fig. 5.1 weToy, Program @ Dete ato each [DSF Pactra Onna Dares Inout Devices Figure 5:1: DSP system with interfacing 5.2 Memory Space Organization: + Memory Space in TMS320CS4xx has 192K words of 16 bits each. Memory is divided into Program Memory, Data Memory and I/O Space, each are of 64K words. ‘© The actual memory and type of memory depends on particular DSP device of the family. + Ifthe memory available on a DSP is not sufficient for an application, it can be interfaced to an external memory as depicted in fig. 5.2a. ‘+ The On- Chip Memory are faster than External Memory. There are no interfacing requirements, Because they are on-chip, power consumption is less and size is small. + Itexhibits better performance by DSP because of better data flow within pipeline, ‘+ The purpose of such memory is to hold Program / Code / Instructions, to hold constant data such as filter coefficients / filter order, also to hold trigonometric tables / kemels of transforms employed in an algorithm. + Not only constants are stored in such memory, they are also used to hold variable data and intermediate results so that the processor need not refer to external memory for the purpose. External memory is off-chip. They are slower memory. Dr. N . Ajay Kumar, Sai Vidya Institute of Technology 1ModuleS_DSPAA External Interfacing is required to establish the communication between the memory and the DSP. They can be with large memory spac The purpose is being to store variable data and as scratch pad memory. Program memory can be ROM, Dual Access RAM (DARAM), Single Access RAM. (SARAM), or a combination of all these. The program memory can be extended externally to 8192K words. That is, 128 pages of 64K words each. The arrangement of memory and DSP in the case of Single Access RAM (SARAM) and Dual Access RAM (DARAM) is shown in fig. 5.2b. One set of address bus and data bus is available in the case of SARAM and two sets of address bus and data bus is available in the case of DARAM. The DSP can thus access two memory locations simultaneously. ‘New Program & Daa ve au if . ac = = Bar Shifter Memory Memory ‘noma memory al Menery Figure.5.2a: Internal memory and interfacing of external memory 655 DSP Memory rt Nemoy Dail sARAM DARAN Figure. 5.2b: SARAM & DARAM Dr. N Ajay Kumar, Sai Vidya Institute of Technology 2ModuleS_DSPAA tice PeeeoPegem iy gg __pa oi ae 2 ert age| 5, | ore oo | = Ce xc Eaat PRR» rep] tity | ee seve | CONS toms | RE wel eee Covenrenis Mok) Miner Mae) ‘natn fr sp DARAM in dauenony ae: AKANE Go EER: ARAN 2040 2EFFH BARAMS Soom oFrrt; —_DARAM®: ADool-BFrRh BARAMS Cooch-Oriti; BARAMT Qiman-PrFER Figure 5.3a Memory map for the TMS320C5416 Brocessor Hex mopam tex Program Progam Hex Poerm 000 x00 00 oy Pe para boat fos jon) exenal taal orerr [OVO oorree omrry| ken 11000) oxcap | 2200] cc | e100 ane] fsa . n es Bete vena ourre carrer oxen] aeeree Fash 2 7 Page ae ae ae eee ‘Adin ne fromctip DARAM progam menory ae: ARAMA oI OI9EFP, DARAMS:014o%b-a1DFEFR DARAMG:O1DoaGbW-OIDEFFR: DARAM?:01¢0008-a1FFFFS ‘Adress ranges orn chip SARAM in program memacy are: SARAMO OZ4000% O29F FR," SARAMI,O2AOOOR-OFBEFFR SARAME d3Co0h-C2DFFFk; SARAMB.O2¢000n 0ZFFFER SARAMA.031000h OJ9FFF: SARAMS:O3A00b-OOBEPPh SARAMGG3COOOh ODEFFR; SRAM?’ O3¢000N-03FFFFR © ‘© Figure 5.3b Extended the memory map for the TMS320C5416 Processor There are 3 bits available in memory mapped register (MMR), PMST for the purpose of on-chip memory mapping, ‘They are microprocessor / microcomputer mode, If this bit is 0, the on-chip ROM is enabled and addressable and if this bit is 1 the on- chip ROM not available. Second bit is OVLY. It implies RAM Overlay. It enables on-chip DARAM data memory blocks to be mapped into program space. If this bit is 0, on-chip RAM is addressable in data space but not in Program Space and if it is 1, on-chip RAM is mapped into Program & Data Space. The third bit is DROM. It enables on-chip DARAM 4-7 to be mapped into data space, If this bit is 0, on-chip DARAM 4-7 is not mapped into data space and if this bit is 1, on-chip DARAM 4-7 is mapped into Data Space. Dr. NAjay Kumar, Sai Vidya Institute of Technology 3ModuleS_DSPAA > > > On-chip data memory is partitioned into several regions as shown in table 5.1 Data memory can be on-chip / off-chip, Table 5.1: Data memory 64K (0000-005F Memory Mapped 96 locations Registers (0060-007F Seratch pad RAM 32 locations (0080-7FFF ‘On-chip DARAM 0-3 32Kx16bit 8000-FFFF ‘On-chip 32K DARAM 4-7 locations, for Data The on-chip memory of TMS320C54xx can be both program & data memory. It enhances speed of program execution by using parallelism. That is, multiple data access capability is provided for concurrent memory operations, The number of operations in single memory access is 3 reads & one write. The external memory to DSP can be interfaced with 16 -23-bit Address Bus, 16-bit Data Bus. Interfacing Signals are generated by the DSP to refer to external memory. The signals required by the memory are typically Chip Select (CS), Output Enable and Write Enable. For example, TMS320C5416 has 16K ROM, 64K DARAM and 64K SARAM. Extended external Program Memory is interfaced with 23 address lines i.c., 8192K locations. The external memory thus interfaced is divided into 128 pages, with 64K words per page. External Bus Interfacing Signals: In DSP there are 16 external bus interfacing signals. The signal is characterized as single bit ie., single line or multiple bits ie., Multiple lines / bus. It can be synchronous / asynchronous with clock. The signal can be active low / active high. It ean be output / input Signal The signal carrying line / lines Can be unidirectional / bidirectional Signal. The characteristics of the signal depend on the purpose it serves. The signals available in TMS320CS4xx are listed in table 5.2 (a) & table 5.2 (b) Dr. [Link] Kumar, Sai Vidya Institute of Technology 4ModuleS_DSPAA Table 5.2 (a) External Bus Interfacing Signals 1 ‘AU-AID 20-bit Address Bus 2 DO-DIS 16-bit Data Bus 3 DS Data Space Select PS Program Space Select 3 is 1/0 Space Select 6 Read/Write Signal 7 MSTRB ‘Memory Strobe 8 TOTRE 1/0 Strobe + In external bus interfacing signals, address bus and data bus are multi-lines bus, ‘Address bus is unidirectional and carries address of the location refereed. © Data bus is bidirectional and carries data to or from DSP. © When data lines are not in use, they are tri-stated. ‘+ Data Space Select, Program Space Select, 1/0 Spac program space or I/O space selection. © These interfacing signals are all active low. They are active during the entire operation of data memory / program memory / 1/0 space reference. Read/Write Signal determines if the DSP is reading the external device or writing, Read/Write Signal is low when DSP is writing and high when DSP is reading, Strobe Interfacing Signals, Memory Strobe and I/O Strobe both are active low. They remain low during the entire read & write operations of memory and VO operations respectively. © External Bus Interfacing Signals from 1-8 are all are unidirectional except Data Bus which is bidirectional. + Address Lines are outgoing signals and all other control signals are also outgoing signals. ect are meant for data space, Table 5.2 (b) External Bus Interfacing Signals 9 READY ‘Data Ready Signal 10 HOLD Hold Request i ‘Hold Acknowledge 12 “Micro State Complete 13 Internupt Request 14 Interrupt Acknowledge 15 External Flag Output 16 ‘Branch Control Input > Data Ready signal is used when a slow device is to be interfaced. > Hold Request and Hold Acknowledge are used in conjunction with DMA controller. Dr. NAjay Kumar, Sai Vidya Institute of Technology 5ModuleS_DSPAA > There are two Interrupt related signals: > Interrupt Request and Interrupt Acknowledge. > Both are active low. > Interrupt Request typically for data exchange. > For example, between ADC / another Processor. > TMS320C5416 has 14 hardware interrupts for the purpose of User interrupt, MeBSP, DMA and timer. > The External Flag is active high, asynchronous and outgoing control signal. > Itinitiates an action or informs about the completion of a transaction to the peripheral device. Branch Control Input is a active low, asynchronous, incoming control signal. > A low on this signal makes the DSP to respond or attend to the peripheral device, > It informs about the completion of a transaction to the DSP. Problem PS.1: What is the range of addresses that can be decoded if A19 is pulled low in ‘a processor with 20 address lin Solution: 20 address lines of processor are AO-A19, With A19 pulled low, effectively there are 19 address lines, Thus, number of addressable locations=2"19=80000h. The range addresses that can be decoded =00000 - 7FFFFh 5.4 The Memory Interface: + The memory is organized as several locations of certain number of bits. ‘The mumber of locations decides the address bus width and memory capacity. + The number of bits per locations decides the data bus width and hence word length. Each location has unique address. © The demand of an application may be such that memory capacity required is more than that available in a memory IC. ‘+ That means there are insufficient words in memory IC. ‘* Or the word length required may be more than that is available in a memory IC. ‘© Thus, there may be insufficient word length. In both the cases, more number of memory ICs ate required. ‘+ Typical signals in a memory device are address bus to carry address of referred memory location + Data bus carries data to or from referred memory location. ‘* Chip Select (CS) Signal selects one or more memory ICs among many memory ICs in the system, Write Enable enables writing of data available on data bus to a memory location * Output Enable (OE) signal enables the availability of data from a memory location onto the data bus. ‘The address bus is unidirectional, carries address into the memory IC. ‘+ Data bus is bidirectional. Chip Select (CS), Write Enable (WE) and Output Enable (OE) control signals are active high or low and they carry signals into the memory ICs, + The task of the memory interface is to use DSP signals and generate the appropriate signals for setting up communication with the memory. Dr. N Ajay Kumar, Sai Vidya Institute of Technology 6ModuleS_DSPAA The logical spacing of interface is shown in fig. 5.4. The timing sequence of memory access is shown in fig. 5.5 There are two read operations, both referring to program memory. Read Signal is high and Program Memory Select is low. There is one Write operation referring to external data memory. Data Memory Select is low and Write Signal low. Read and write are to memory device and hence memory strobe is low. * Intemnal program memory reads take one clock cycle and External data memory access require two clock cycles, TMS320C5416 wees reverie} xt a2 AOAR popis 16 | oonis Mamery a meriace WE ‘OE ve Si S mere CLKOUT Address XXX > Data R/W Figure. 5.5 Timing Sequence for External Memory Access or Memory interface signals for a read-read-write sequence of operations. + To Interface Slower off-chip Memory & I/O wait states are required. User accessible Memory Mapped Software Wait State Register (SWWSR) is used for the Purpose. Dr. N Ajay kumar, Sai Vidya Institute of Technology 7ModuleS_DSPAA + Thete is no need for external hardware to insert wait states. 3-bit Field in SWWSR are meant for indicating number of wait states. 000 implies no wait state and 111 implies seven wait states ‘© However, wait states are applicable to program & data memory of 2 pages each of 32K words and to I/O space of one page of 64K. ‘+ Further to interface devices requiring more than 7 wait states, hardware READY Signal is used, + External Device sends signal on READY line to the DSP to indicate its readiness for transaction. Problem PS.2: Up to what limit can the program memory be extended in a processor with 20 address lines? How must the extended memory be organized to for addressing by a C54xx Processor? Solution: With 20 address lines, the program memory can be extended to 2°20 locations=100000 h. ‘Memory may be organized into several pages of 64K words each. Number of pages = 2°20 / 64K = 2°20 / (246 x2°10) = 16 pages Problem P5.3: 256K x 16-bit RAM is interfaced to the DSP Processor with A17 address line of the memory device connected to Program Space Select line. Determine the total Program ‘memory and Data Memory Addressable. Solution: ‘64K words of Memory is for the purpose of data (not more than that). As Program Space select line is connected to 17, it makes number of addressable locations = 2917 = 128K words. Remaining 256K (64K=128K) =64K is unused. Problem PS.4: Is it possible to connect amemory device without Decode (interfacing) Circuit? If so, connect 8k x 16 SRAM to TMS320CS4x. What are the merits & demerits of the solution? Solution: ‘The interfacing circuit is shown in fig. PS.4. 8K x 16 SRAM to be interfaced. ‘The address lines are A19 AI8.....[A12 All A10 A9 A8 AT AG AS Ad A3A2 Al AO] Address lines required: AO-A12. Address range is 0000-1 FFFh, Effects of ‘No decode’ interface are st memory Access ENTIRE Address space is used by the Device that is connected + Memory responds to 0000-1FFFh and also to all combinations of address bits A13-A19 (In the example quoted) + Program space select & data space select lines are not used. + SRAM is thus indistinguishable as a program or data Memory Dr. N Ajay Kumar, Sai Vidya Institute of Technology 8ModuleS_DSPAA ‘TMS320C54 SRAM AO-A22 ES AO-A12 16 Do-Di5 Do-Dis STF cs Vee MPC Ry Wwe Fig. P5.4: Memory interface without decode circuit Problem PS.S: Design an interface to connect a 64K x 16 flash memory to a TMS320CS4x device. The Processor address bus to be used is A0-A15. The flash memory has the signals as shown in fig. P: Solution: Address lines from A0-A15 are used to address 64K. locations. All the data lines, DO-D15 are used to carry data word. Data Space Select line is connected to chip enable of memory so that whenever DSP refers to data memory, this flash memory is enabled. When DSP refers to memory and it isa write operation, both memory strobe and read/write signals will be low. They are combined in using OR gate and used as write enable for memory. ‘Memory read is performed by combining memory strobe and XF signals. AoAis De-Dis Vee Figure PS.5: Interfacing flash memory Dr. N Ajay Kumar, Sai Vidya Institute of Technology 9ModuleS_DSPAA Problem PS. a C5416. U Design a data memory system with address range 000800h-O00FFFh for ¢ 2K x 8 RAM memory chips Solution: ‘+ Memory capacity: 2K. Memory word length: 8 bits < that of the processor. + Word length needs to be extended to 16 bits. 2 memory ICs of same capacity are required. One IC is used to hold LS byte of the data and the other IC to hold MS byte. + Both ICs are selected simultaneously and are given all other control signals, together. ‘+ Data bus of DSP is split into two halves, LS and MS byte and they are connected to respective ICs, ‘© Address bus of DSP from A0-A10 are connected to both the ICs, Whenever DSP issues an address and issues appropriate read / write control signals, both the ICs respond simultaneously. ‘The remaining lines of address bus, A11-A22 are used for the purpose of decoding © The arrangement of ICs for extension of memory word length is shown in fig. P5.6. Fig. P5.6: Extending the word length Problem P§.7: Interface an 8K x 16 ROM to the C5416 DSI TEFFFh, in the address range 7FE000h- Doe AAs Figure PS.7 Interfacing ROM Dr. N Ajay Kumar, Sai Vidya Institute of Technology 10ModuleS_DSPAA Problem PS.8: Design a circuit to interface 4K x 16 and a 2K x 16 memory chip to realize program memory space for the TMS320C54xx processor in the address Ranges 03F000h- O3FFFFh and 05F800h-OSFFFFh, respectively. Solution: 4K x 16 with address range 03F000h-03FFFFh, Address lines: 12 in number: AIL-A0. Remaining Address lines: 11 in umber: A22-A12 out of which A22-A18 all zet0s, AI7-A12 all ones. 2K x 16 with address range 0SF800h-OSFFFFh. Address lines: 11 in number: A10-A0, Remaining Address lines: 12 in number: A22-A11 out of which A22-A19 and A17 all zeros, A16-A11 and A18 all ones. Connect the memory and design the decoding logic accordingly. Problem P5.9: Design a circuit to interface 64K words of the program memory space from OFFFFFh-0F0000h for the TMS320C5416 processor using 16K x 16 memory chips. Solution: 64K. required > the memory capacity of IC. The memory capacity needs to be extended. 4 Memory ICs are required. Address lines for 16K> 14 in number: A13-A0. Remaining Address lines: 9 in number: A22-A14, A22-A20 all zeros, A19-A16 all ones, Address on A15-A14 vary from 00 to 11. (4 combinations). Fig. P5.9: Interfacing memory to extend capacity 5.5 Parallel /O Interface: ‘+ Parallel /O ports are used for interfacing external device, such as ADC, DAC to DSP processor. + Accessing 1/0 requires use of PORTR AND PORTW instructions © PORTR is used read a peripheral connected to an input port. The data read is placed in the specified data memory location. Dr. N Ajay Kumar, Sai Vidya Institute of Technology uwModuleS_DSPAA + Similarly we have PORTW is used to send contents of the specified data memory location to ana output port The timing diagram in fig, 5.6 shows the signals that are involved in an I/O transaction, The processor uses [5 signal to indicate an I/O operation. Two eycles are required for 1/0 read and write operation, During these operations, the signal TOSTRB remains low. This signal can be used to control the output enables of the external device used to implement the input output ports. © Similar to a memory interface circuit, wait States can be inserted to interface slow peripherals + VO devices are interfaced to DSP using unconditional 1/0 mode, programmed I/O mode or interrupt /0 mode. * Unconditional 1/0 does not require any handshaking signals. ‘* DSP assumes the readiness of the I/O and transfers the data with its own speed. + Programmed 1/O requires handshaking signals, ‘+ DSP waits for the readiness of the I/O readiness signal which is one of the handshaking signals * After the completion of transaction DSP conveys the same to the I/O through another handshaking signal. ‘+ Interrupt 1/0 also requires handshaking signals. DSP is interrupted by the I/O indicating the readiness of the 1/0, DSP acknowledges the interrupt, attends to the interrupt, Thus, DSP need not wait for the /O to respond, Itcan engage itself in execution as long as there is no interrupt Fig, 5.6: Read-Write-Read Sequence of Operations Dr. N Ajay Kumar, Sai Vidya Institute of Technology 2ModuleS_DSPAA 5.6: Programmed I /O interfac ‘+ In this method the CPU keeps pulling the external device and itis ready for transmitting or receiving data + Software polling is used in programmed 1/0 to ascertain the readiness of the external device for a data transfer to and from the processor * VO strobe and 1/0 space select are issued by the DSP. Two clock cycles each are required for /O read and 1/0 write operations. ‘+ An example of interfacing ADC to DSP in programmed /0 mode is shown in fig. 5.7. * ADC has a start of conversion (SOC) signal which initiates the conversion. ‘In programmed I/O mode, external flag signal is issued by DSP to start the conversion, Ay Aus Address —_ decoder — IS |}-—} —*| RD RW DSP ADC DeD, DeDis Analog In me — Ve xp 80 + MP/MIC_ BIO }’———————| Eo Fig. 5.7; ADC in Programmed 1/0 mode + CS4XX has two register namely GPIOCR and GPIOSCR. + GPIOCR is general purpose Input Output register that is used to program signals for input output interfacing. + GPIOSCR isa satus register used to read the status of the handshake signals + CS4xxfiamily has at least two dedicated pins for performing the 10 operations. + these signals ate B7O and XF. + B10 isan input to the processor XF is ouput + Using software, BTO can be used to monitor the status of an extemal peripheral + The XP signal is used to contol the peripheral + This mode of communication using B7O and XF signals asynchronous and is helpful for making the processor communicate with the deviees that ae slower than the processor itself. # Data length can be 8 bits or 16 bits. + On detecting the low BTO, the processor reads the peripheral data using the PORTR instruction + Intum, it informs the peripherals VIA XF about the completion ofthe transaction allowing the processor to initiate the next transfer. + Figure 5.7 shows the example of interface between an A/D converter and DSP processor in the program and VO mode. Dr. N Ajay Kumar, Sai Vidya Institute of Technology BModuleS_DSPAA (start ADC) XF is used to start the A/D conversion and BTO, is used to determine its completion before the data is read. The flowchart of the algorithm to implement the software polling used by the processor to communicate with the ADC is shown in figure 5.8 The critical consideration in the implementation of the scheme is used to control the time between any two consecutive XF or SOC pulses this time is the sampling interval and must romain constant for aal the samples, Conversion over Read sample from ADC t Store, Process save Processed sample ¥ Wait for sampling interval & XP=1,wait, XF=0 no RIO seen | Fig. 5.8: Flow chart of the diagram for software polling for the Programmed I/O interface of figs.9 5.7 Interrupt VO: This mode of interfacing }O devices also requires handshaking signals. DSP is interrupted by the I/O whenever it is ready. DSP Acknowledges the interrupt, after testing certain conditions, attends to the interrupt. DSP need not wait for the 1/0 to respond. It can engage itself in execution. T here are a variety of interrupts. One of the classifications is maskable and non- maskable Ifmaskable, DSP can ignore when that interrupt is masked. Another classification is vectored and non-vectored. If vectored, Interrupt Service subroutine (ISR) is in specific location. In Software Interrupt, instruction is written in the program, In Hardware interrupt, a hardware pin, on the DSP IC will receive an interrupt by the external device. Hardware interrupt is also referred to as external interrupt and software interrupt is referred to as internal interrupt. Internal interrupt may also be due to execution of certain instruction can causing interrupt. In TMS320CS4xx there are total of 30 interrupts. Reset, Non-maskable, Timer Interrupt, HPI, one each, 14 Software Interrupts, 4 External user Interrupts, 6 McBSP related Interrupts and 2 DMA related Interrupts Dr. N Ajay Kumar, Sai Vidya Institute of Technology 4ModuleS_DSPAA Host Port Interface (HPI) is a 8 bit parallel port It is possible to interface to a Host Processor using HPL Information exchange is through on-chip memory of DSP which is also accessible Host processor. Registers used in managing interrupts are Interrupt flag Register (IFR) and Interrupt Mask Register (IMR), IFR maintains pending external & internal interrupts. One in any bit position implies pending interrupt. Once an interrupt is received, the corresponding bit is set. IMR is used to mask or unmask an interrupt. One implies that the corresponding interrupt is unmasked. Both these registers are Memory Mapped Registers. One flag, Global enable bit (INTM), in STI register is used to enable or disable all interrupts globally. If INTM is zero, all unmasked interrupts are enabled Ifit is one, all maskable interrupts are disabled. When an interrupt is received by the DSP, it checks if the interrupt is maskable. If the interrupt is non-maskable, DSP issues the interrupt acknowledgement and thus serves the interrupt. If the interrupt is hardware interrupt, global enable bit is set so that no other interrupts are entertained by the DSP. Ifthe interrupt is maskable, status of the INTM is checked, If INTM is 1, DSP does not respond to the interrupt and it continues with program execution, If the INTM is 0, bit in IMR register corresponding to the interrupt is checked. If that bit is 0, implying that the interrupt is masked, DSP does not respond to the interrupt and continues with its program execution. Ifthe interrupt is unmasked, then DSP issues interrupt acknowledgement. Before branching to the interrupt service routine, DSP saves the PC onto the stack. The same will be reloaded after attending the interrupt so as to return to the program that has been interrupted. The response of DSP to an Interrupt is shown in flow chart in fig. 5.9. Dr. N Ajay Kumar, Sai Vidya Institute of Technology 15ModuleS_DSPAA Interrupt request received No Maskable? > TW or SW interrupe? PC saved on stack q ISR executed q Return instruction restores PC No] Interrupt acknowledged ‘Main program continues Fig. 5.9: Response of DSP to interrupt Problem P5.10: Interface the TMS320C54xx to a 10 bit ADC and an 8 bit DAC, The sampled signal read from the ADC is to be written to the DAC after adjusting its size (to 8 bits). The start of conversion is to be initiated by the TOUT signal of the timer available on DsP. Solution: Initialize processor with respect to desired speed, internal registers: PMST, BSCR, SWWSR. Initialize internal timer for sampling period of ADC. Apply analog input signal. Send start conversion through TOUT. Continue with any other program execution. ADC interrupts DSP after conversion on INTI. DSP reads 10 bit data and converts to 8 bit by shifting to right. It then processes the sample and sends this data to DAC. DAC converts the data back to analog. itt NTT TouT te IcSTART etxout | dferkin — anatog in lesTey RD [ADC RW a cs DsDp Ds DgD> outt oe ArAis Adcr WR DAS cososer WR out2 Fig, P5.10: Interfacing DSP to ADC & DAC Dr. N Ajay Kumar, Sai Vidya Institute of Technology 16ModuleS_DSPAA ect Memory Access (DMA) operation: In any application, there is data transfer between DSP and memory and also DSP and VO device, as shown in fig. 5.10. However, there may be need for transfer of large amount of data between two memory regions or between memory and 1/0. DSP can be involved in such transfer, as shown in fig. 5.11 Since amount of data is large, it will engage DSP in data transfer task for along time. DSP thus will not get utilized for the purpose it is meant for, ic, data manipulation. The intervention of DSP has to be avoided for two reasons: to utilize DSP for useful signal processing task and to increase the speed of transfer by direct data transfer between memory or memory and 1/0. The direct data transfer is referred to as direct memory access (DMA) The arrangement expected is shown in fig. 5.12. DMA controller helps in data transfer instead of DSP. Fig. 5.10: Interface between DSP and external devices Int Memory | DsP ks] Memory Memory kt==s DSP f= I/O Fig, 5.11: Data transfer with intervention by DSP. Dr. N AjayKumar , Sai Vidya Institute of Technology v7ModuleS_DSPAA vvvyv vvy v vVovvv v vv vv v Memory Memory Memory (LY vo (LY Fig. 5.12: data transfer without intervention by DSP In DMA, data transfer can be between memory and peripherals which are either intemal or extemal devices DMA controller manages DMA operation. Thus DSP is relieved of the task of data transfer. Because of direct transfer, speed of transfer is high. In TMS320C54xx, there are up to 6 independent programmable DMA channels. Each channel is between certain source & destination. One channel at a time can be used for data transfer and not all six simultaneously. These channels can be prioritized. The speed of transfer measured in terms of number of clock cycles for one DMA transfer depends on several factors such as source and destination location, external interface conditions, number of active DMA channels, wait states and bank switching time. The time for data transfer between two internal memory is 4 eycles for each word. Requirements of maintaining a channel are source & Destination address for a channel, separately for each channel Data transfer is in the form of block, with each block having frames of 16 / 32 bits. Block size, frame size, data are programmable. Along with these, mode of transfer and assignment of priorities to different channels are also to be maintained for the purpose of data transfer There are five, channel context registers for each DMA channel. They are Source Address Register (DMSRC), Destination Address Register (DMDST), Element Count Register (DMCTR), Syne select & Frame Count register (DMSFC), Transfer Mode Control Register (DMMCR). There are four reload registers. ‘The context register DMSRC & DMDST are source & destination address holders. DMCTR is for holding mumber of data elements in a frame. DMSFC is to convey sync event to use to trigger DMA transfer, word size for transfer and for holding frame count. DMMCR Controls transfer mode by specifying source and destination spaces as program memory, data memory or I/O space. Source address reload & Destination address reload are useful in reloading source address and destination address, Similarly, count reload and frame count reload are used in reloading count and frame count. Additional registers for DMA that are common to all channels are Source Program page address, DMSRCP, Destination Program page address, DMDSTP, Element index address register, Frame index address register. Dr. N Ajay Kumar Sai Vidya Institute of Technology 18ModuleS_DSPAA Number of memory mapped registers for DMA are 6x(5+4) and some common registers for all channels, amounting to total of 62 registers required. However, only 3 (=I for priority related) are available, They are DMA Priority & Enable Control Register (DMPREC), DMA sub bank Address Register (DMSA), DMA sub bank Data Register with auto increment (DMSDI and DMA sub bank Data Register (DMSDN). To access each of the DMA Registers Register sub addressing Technique is employed. The schematic of the arrangement is shown in fig. 5.13. A set of DMA registers of all channels (62) are made available in set of memory locations called sub bank This avoids the need for 62 memory mapped registers. Contents of either DMSDI or DMSDN indicate the code (1’s & 0's) to be written fora DMA register and contents of DMSA refers to the unique sub address of DMA register to be accessed, Mux routes either DMSDI or DMSDN to the sub bank. The memory location to be written DMSDI is used when an automatic increment of the sub address is required after each access. Thus it can be used to configure the entire set of registers DMSDN is used when single DMA register access is required. The following examples bring out clearly the method of accessing the DMA registers and transfer of data in DMA mode Fig. 5.13: Register Subaddress Technique Problem P5.11: For a TMS320C54xx operating at a clock frequency of 100MHz, how many 16 bit data elements can be transferred between two internal memory locations per second in DMA mode? Solution: Clock cycle period=1/(100x10°6)-0.01x10%-6 s (given) ‘Number of clock cycles per transfer of single 16 bit data element = 4 eycles (known) Time for transferring single data element = 4 x 0.01x10*-6 s Number of data elements transferred per second= 1/(4 x 0.01x10*-6)}=25x10°6 data elements Dr. N Ajay Kumar, Sai Vidya Institute of Technology 19ModuleS_DSPAA UNIT 2: Interfacing and Applications of DSP Processor 5.9. Introduction: * Inthe case of parallel peripheral interface, the data word will be transferred with all the bits together. + In addition to parallel peripheral interface, there is a need for interfacing serial peripherals. DSP has provision of interfacing serial devices too. 5.10. Synchronous Serial Interface: ‘There are certain 1/0 devices which handle transfer of one bit at a time. Such devices are referred to as serial I/O devices or peripherals. * Communication with serial peripherals can be synchronous, with processor clock as reference of it can be asynchronous. ‘Synchronous serial interface (SSI) makes communication a fast serial communication and asynchronous mode of communication is slow serial communication. ‘+ However, in comparison with parallel peripheral interface, the SSI is slow. The time taken depends on the number of bits in the data word. FS* CODEC ‘CLK Fig, 5.14: SSI between DSP & CODEC device 5.11 CODEC Interface Cireuit: CODEC, a coder-decoder is an example for synchronous serial 1/0. Ithas analog input-output, ADC and DAC. The signals in SSI generated by the DSP are DX: Data Transmit to CODEC, DR: Data Receive from CODE CLKX: Transmit data with this clock reference, CLER: Receive data with this clock reference, Dr. N Ajay amar, Sai Vidya Institute of Technology 20ModuleS_DSPAA FSX: Frame syne signal for transmit, FSR: Frame syne signal for receive, First bit, during transmission or reception, is in syne with these signals, RRDY: indicator for receiving all bits of data and XRDY: indicator for transmitting all bits of data Similarly, on the CODEC side, signals are FS*: Frame syne signal, DIN: Data Receive from DSP, DOUT: Data Transmit to DSP and SCLK: Tx / Rx data with this clock reference. ‘+ The block diagram depicting the interface between TMS320CS4x and CODEC is shown in fig, 5.14, ‘© Asonly one signal each is available on CODEC for clock and frame synchronization, the related DSP side signals are connected together to clock and frame syne signals on CODEC. Fig. 5.15 and fig. 5.16 show the timings for receive and transmit in SSI, respectively. OLKX DNRI to NEL copy(E) ——Wete 2 DKRICC) DRI to DNR copy(C) Weiteto DRE Fig 5.16: Transmit operation timing for SSI ‘+ As shown, the receiving or transmit activity is initiated at the rising edge of cloc! CLKR/CLKX. Dr. N Ajay Kumar, Sai Vidya Institute of Technology 2ModuleS_DSPAA Reception / Transfer starts after FSR / FSX remains high for one clock cycle. + RRDY / XRDY is initially high, goes LOW to HIGH after the completion of data transfer. Each transfer of bit requires one clock cycle. Thus, time required to transfer / receive data word depends on the number of bits in the data word. An example of data word of 8 bits is shown in the fig. 5.15 and fig. 5.16 Fig. 5.17 shows the block diagram of PCM3002 CODEC. Analog front end samples signal at 64X over sampling rate. It eliminates need for sample-and-hold circuit and simplifies need for anti-aliasing filter. ADC is based on Delta-sigma modulator to convert analog signal to digital form, * Decimation filter reduces the sampling rate and thus processing does not need high speed devices. DAC is Delta-sigma modulator, converts digital signal to analog signal Interpolation increases the sampling rate back to original value. LPF smoothens the analog reconstructed signal by removing high frequency components, The Serial Interface monitors serial data transfer. It accepts built-in ADC output and converts to serial data and transmits the same on DOUT. It also accepts serial data on DIN & gives the same to DAC. The serial interface works in synchronization with BCLKIN & LRCIN. The Mode Control initializes the serial data transfer It sets all the desired modes, the number of bits and the mode Control Signals, MD, MC and ML. MD carries Mode Word. MC is the mode Clock Signal ‘MD to be loaded is sent with reference to this clock, ML is the mode Load Signal. It defines start and end of latching bits into CODEC device. Deta-sigma Digial vet ‘aioe L,| “todutator’ |.) pecimation | [Serial] pista Reh in >| ‘ier 2 « [Pisin Lenow | EFS] [Matitever Disa Mode enoutel Gutpor |, Deitasiema || inempotation fg] comret Renou 2} baller modulator Tier seviat * Syst nos clock Fig. 5.17: Block diagram for CODEC PCM3002 ‘Figure 5 .17shows interfacing of PCM3002 to DSP in DSK. ‘DSP is connected to PCM3002 through McBSP2. + The same port can be connected to HPI. Mux selects one among these two based on CPLD signal Dr. N Ajay Kumar, Sai Vidya Institute of Technology 2ModuleS_DSPAA + CPLD in Interface also provides system clock for DSP and for CODEC, Mode control signals for CODEC. © CPLD generates BCLKIN and LRCIN signals required for serial interface. TMS320VC5416 HPI I PCM3002 Mepsp2 [*| Mux [| DIN +1 i] pouT LRCIN le | DSP bus le +| 1 BCLKIN cPLD SYS_CLK 12.288MHz. |_| [> OSCR | —__4 4} controt Mic, _ | Interface MD Fig. 5.18: PCM3003 Interface to DSP in DSK * PCM3002 CODEC handles data size of 16 / 20 bits. It has 64x over-sampling, delta sigma ADC & DAC. + Ithas two channels, called left and right. The CODEC is programmable for digital de- emphasis, digital attenuation, soft mute, digital loop back, power-down mode. ‘System clock, SYSCLK of CODEC can be 25665, 384f5 or 512f8, + Internal clock is always 2561 for converters, digital filters. ‘+ DIN, DOUT are the single line data lines to carry the data into the CODEC and from CODEC. ‘© Another signal BCLKIN is data bit clock, the default value of which is CODEC SYSCLK / 4. LRCIN is frame sync signal for Left and Right Channels. + The frequency of this signal is same as the sampling frequency. ‘© The default divide factor can be 2, 4, 6 and 8, © Thus, sampling rate is minimum of 6 KHz and maximum of 48 KHz. Problem P5.12: A PCM3002 is programmed for the 12 KHz sampling rate, Determine the divisor N that should be written to the CPLD of the DSK and the various clock frequencies for the set up. Solution: CPLD input Clock=12.288MIIz (known) Sampling rate f=CODEC_SYSCLK / 256 =12KHz (given) CPLD output clock, CODEC_SYSCLK =12.288 x 106 / N Dr. N Ajay Kumar, Sai Vidya Institute of Technology 23ModuleS_DSPAA Thus, CODEC_SYSCLK =256 x 12 KHz 8 N=12.288 x 106/(256 x 12 x 103) =4 Problem PS.13: Determine the timing parameters for a 20 bit data communication at 8KHz. Solution: CPLD input Clock=12.288MHz (known) ‘Sampling rate fs-8KHz (given) Proceeding as in previous problem, N=6 Thus, CODEC_SYSCLK=2.048MHz BCLKIN, Bit clock rate=CODEC_S LRCIN=fs-8KHz, ‘SCLK / 12KHz Problem PS.14: Frame Sync is generated by dividing the 8.192MHz clock by 256 for the serial communication, Determine the sampling rate and the time a 16 bit sample takes when transmitted on the data line Solution: LRCIN, Frame Sync = 8.192x106/256 =32 KHz Sampling rate f= frequency of LRCIN-32 KHz BCLKIN, Bit clock rate=CODEC_SYSCLK / LRCIN, Frame Syne = 8.192x10°6/256 =32 KHz ‘Sampling rate f= frequency of LRCIN=32 KHz BCLKIN, Bit clock rate-CODEC_SYSCLK / 4-8,192x10°6/4-2.048MHz Bit clock period= 1/2.048x10°6 -0.488x10"-6s Time for transmitting 16 bits ~0.488x10"-6x16 =7.8125x10*-6s (refer fig. P8.3) The CODEC PCM3002 supports four data formats as listed in table 5.3, The four data formats depend on the number of bits in the data word, if the data is right justified or left justified with respect to LRCIN and if it is 12S (Integrated Inter-chip Sound) format. 192x106/4=2.048MHz ‘© Table 5.3: Data formats of CODEC Tomar DAC KDE fecemat ie bit MSE firs right jus fe bk, MSH fist, lefts Jrcemat tbo bit, MSH fi right justtiog)20 bit, MSB first, tet justified Jkcemat 4 20 bit MSH Hint, te justified Po bi, MSB Hist, tet jusuifie frcomat] 206i, MSH fs BS 20 iL MSH fies, BS Figure 5.18 and fig. 5.19 depicts the data transaction for CODEC PCM3002. As shown in fig(5.19) DIN (/ DOUT) carries the data. BCLKIN is the reference for transfer When LRCIN is high, left channel inputs (/ outputs) the data and when LRCIN is low, right channel inputs (/ outputs) the data The data bits at the end (/ beginning) of the LRCIN thus Right (/ left) justified Dr. N Ajay Kumar, Dept. of ECE,SVIT 24ModuleS_DSPAA BCLKIN pouT Me Tor 16bits Fig. PS.3: Time for Data Transmission a (DAC, 16 Dit/MSB first sight justified) Fig. 5.19: Data Formats for PCM3002 Another data format handled by PCM3002 is ’S (Integrated Inter-chip Sound). It is used for transferring PCM between CD transport & DAC in CD player. LRCIN is low for left channel and high for right channel in this mode of transfer During the first BCKIN, there is no transmission by ADC. During 2nd BCKIN onwards, there is transmission with MSB first and LSB last. Left channel data is handled first followed by right channel data. A 18B, Fig, 5.20: ADC 20 bit, MSB first, P'S format Dr.N Ajay Kumar, Sai Vidya Institute of Technology 25ModuleS_DSPAA 5.12 DSP Based Bio-telemetry Receiver: ‘+ Biotelemetry involves transfer of physiological information from one remote place to another for the purpose of obtaining experts opinion * The receiver uses radio Frequency links. + The schematic diagram of biotelemetry receiver is shown in fig. 5.21 ‘+ The biological signals may be single dimensional signals such as ECG and EEG or two- dimensional signals such as an image, i.., X-ray. Signal can even be multi-dimensional signal i.e., 3D picture. ©The signals at source are encoded, modulated and transmitted. ‘+ The signals at destination are decoded, demodulated and analysed. “Lena LD mare | [08 Ber Processing 1) interface z Malipe cham! DAC Feork Fig. 5.21: Bio-telemetry Receiver ‘© An example of processing ECG signal is considered. * The scheme involves modulation of ECG signal by employing Pulse Position Modulation (PPM). ‘+ Atthe receiving end, it is demodulated. This is followed by determination of Heart beat Rate (HR), ‘* PPM Signal either encodes single or multiple signals. The principle of modulation being that the position of pulse decides the sample value. + The PPM signal with two ECG signals encoded is shown in fig. 5.22. © The transmission requires a syne signal which has 2 pulses of equal interval to mark beginning of a cycle. + The sync pulses are followed by certain time gap based on the amplitude of the sample of Ist signal to be transmitted. + Atthe end of this time interval there is another pulse. ‘© This is again followed by time gap based on the amplitude of the sample of the 2nd signal to be transmitted. + After encoding all the samples, there is a compensation time gap followed by syne pulses to mark the beginning of next set of samples. ‘Third signal may be encoded in either of the intervals of Ist or 2nd signal. ‘© With two signals encoded and the pulse width as tp, the total time duration is Stp. ‘Since the time gap between the pulses represent the sample value, at the receiving end the ‘time gap has to be measured and the value so obtained has to be translated to sample value. Dr. N Ajay Kumar, Sai Vidya Institute of Technology 26ModuleS_DSPAA Decoding scheme for the PPM Receiver. The scheme for decoding is shown in fig. 5.23. DSP Internal Timer employed. «The pulses in PPM generate interrupt signals for DSP. The interrupt start / terminate the timer. ‘+ The count in the timer is equivalent to the sample value that has been encoded, © Thus, ADC is avoided while decoding the PPM signal. be Sync {¢——, ——9} t — oa snc pulses ‘ ‘pulses ig each pulse interval 1: pulse interval corresponding to sample value of 1* signal (x: pulse interval corresponding to sample value of 2™ signal ‘o: compensation time interval Fig. 5.22: A PPM signal with two ECG signals p a rs oT = Interrupts. ' i fnsye ce Fig. 5.23: Decoding PPM signal with two ECG signals jotelemetry Receiver Implementation: DSP based PPM signal decoding is shown in fig. 5.24, ‘+ PPM signal interface generates the interrupt for DSP. DSP entertains the interrupt and starts a timer. © When it receives another interrupt, it stops the timer and the count is treated as the digital equivalent of the sample value. ‘+ The process repeats. Dual DAC converts two signals encoded into analog signals. ‘+ And heart rate is determined referring to the ECG obtained by decoding, ‘© Heart Rate (HR) is a measure of time interval between QRS complexes in ECG signal, Dr. N Ajay Kumar, Sai Vidya Institute of Technology 7ModuleS_DSPAA PPM Input QRS complex in ECG is an important segment representing the heart beat. There is periodicity in its appearance indicating the heart rate. The algorithm is based on Ist and 2nd order absolute derivatives of the ECG signal, Since absolute value of derivative is taken, the filter will be a nonlinear filtering, \TMS320C5402 PPM Daa [o> ECG Signal tnterupe [| Dac) Bus I> ie Interface Request Interface | [qECh536 Fig. 5.24: DSP based biotelemetry Receiver Implementation ECG signal Processing for Heart rate determination Let the Ist order derivative be yl(n) = x(n) -x(n-1) And let the 2nd order derivative be y2(n) = x(n -2)- 2x(n -1) + x(n) The Ist order derivative is obtained as the difference between the two adjacent samples, the present sample and the previous sample. In a similar way, 2nd order derivative is obtained by finding the derivative of Ist order derivative. The yI(n) and y2(n) are summed. & y3(n) = yl(n) = y2(n) High frequency components are removed from y3(n) by passing the same through a LPF to get y4(n) ~aly3(n) = 4(n -1)) + y(n -1) Mean of half of peak amplitudes is determined, which is threshold for detection of QRS complex. QRS interval is then the time interval between two such peaks. Time Interval between two peaks is determined using internal timer of DSP. Heart Rate, heart beat per minute is computed using the relation HR=Sampling rate x 60 / QRS interval. The signals at various stages are shown in fig. 5.25 Dr. N Ajay Kumar, Sai Vidya Institute of Technology 28ModuleS_DSPAA QU gL Fig. 5.25: Signals in determination of HR 5.13 A Speech Processing System: ‘© The purpose of speech processing is for analysis, transmission or reception as in the case of radio / TV / phone, denoising, compression and so on. + There are various applications of speech processing which include identification and verification of speaker, speech synthesis, voice to text conversion and vice versa and so on. ‘+ Aspeech processing system has a vocoder, a voice coding / decoding circuit. Schematic of speech production is shown in fig. 5.26. MUSCLE FoRCE NASALTRACT — NOSTRIL LUNGS TRACHEA VOCAL. ©—VOCALTRACT. «OUTIL BRONCHI CORDS Fig, 5.26: Speech Production Mechanism ‘© The vocal tract has vocal cord at one end and mouth at the other end. The shape of the vocal tract depends on position of lips, jaws, tongue and the velum, Dr. N Ajay Kumar, Sai Vidya Institute of Technology 29ModuleS_DSPAA It decides the sound that is produced. There is another tract, nasal tract. Movement of velum connects or disconnects nasal tract. The overall voice that sounds depends on both, the vocal tract and nasal tract. Two types of speech are voiced sound and unvoiced sound. ‘Vocal tract is excited with quasi periodic pulses of air pressure caused by vibration of vocal cords resulting in voiced sound. Unvoiced sound is produced by forcing air through the constriction, formed somewhere in the vocal tract and creating turbulence that produces source of noise to excite the vocal tract. By the understanding of speech production mechanism, a speech production model representing the same is shown in fig. 5.27. SO-HG + Fig. 5.27: Speech Production Model Pulse train generator generates periodic pulse train. Thus it represents the voiced speech signal. Noise generator represents unvoiced speech. ‘Vocal tract system is supplied either with periodic pulse train or noise. The final output is the synthesized speech signal, Sequence of peaks occurs periodically in voiced speech and it is the fundamental frequency of speech The fundamental frequency of speech differs from person to person and hence sound of speech differs from person to person. Speech is a nonstationary signal. However, it can be considered to be relatively stationary in the intervals of 20ms. Fundamental frequency of speech can be determined by autocorrelation method. In other words, itis a method of determination of pitch period. Periodicity in autocorrelation is because of the fundamental frequency of speech. A three-level clipping scheme is discussed here to measure the fundamental frequency of speech. The block diagram for the same is shown in fig. 5.28. Dr. N Ajay Kumar, Sai Vidya Institute of Technology 30ModuleS_DSPAA [Simei Comer clipper, fine “Autocorrelation Find postion, vatue of [>| Compare peak lee wa ee Heme Be aon omnmeiaredld Fig, 5.28: Block Diagram of Clipping Autocorrelation Pitch Detector Autocorrelation Computatior ‘The autocorrelation of y(n) is computed which will be 0,1 or -1 as defined by eq. (1). Rk) = Do y(ntm)y(n+m+k) e if yint+m)=0 or y(nt+m+k)=0 Lif y(ntm)= vine m+k) a Lif yintm)# vintm>k) wnt m)ynem-+k) ‘The three-level clipping scheme ii estimation is explained below + The speech signal s(t) is filtered to retain frequencies up to 900Hz and sampled using ADC to get sin), + The sampled signal is processed by dividing it into set of samples of 30ms duration with 20ms overlap of the windows, + The average of absolute magnitudes is computed with a hundred sample rectangular window. shown in figure 5.29, The algorithm for which period Dr. N Ajay Kumar, Sai Vidya Institute of Technology aModuleS_DSPAA + The peak signal level in each frame is compared to a threshold determined by measuring the peak signal level for 50ms of background noise as shown in the block “compute silence level threshold” in the block diagram. ‘+ Ifthe peak signal level is above the threshold signifying that the segment is speech not noise, then the algorithm proceeds as follows otherwise the segment is clarified as silence and no further action is taken The clipping level, is determined as a fixed percentage (78%) of the minimum and maximum, absolute values in the first and last hundred samples of speech segment. Using the clipping level, the speech signal is produced by a three-level Centre clipper and correlation function is computed over the range of the expected range of pitch periods. ‘The largest peak of the autocorrelation function is located and the peak value is compared to a fixed threshold example 30% of Rn (0) If the false below threshold segment is classified as a unvoiced, if itis above the threshold, the pitch period is defined as the location of the largest peak. Inpatsamptes Fig, 5.29: Three level Center Clipped signal\ Implementation of speech processing on the TMS320 C54XX processor. Speech samples were recorded using voice recorder software in Windows 98 the signal was sampled at 16 kilohertz in 16-bit mono format. The autocorrelation module is the most computation intensive section of pitch detection for this reason and DSP was used to compute A 400-point autocorrelation for a 480-sample segment. For the sampling frequency of 16 kilohertz 30 seconds of speech corresponding to 480 samples and it takes about 17200 clock cycles are 0.17 milliseconds for the tms320 C5402 running at 100 megahertz Timing can be improved by using lower sampling rate and thereby reducing the section size reduction of the window size for computation of autocorrelation or using adaptive methods for determining the frame size will further reduce the competition involved figure 5.30 shows the autocorrelation output of a voice speech signal and figureS.31 that of an unknown speech signal. Dr. N Ajay Kumar, Sai Vidya Institute of Technology 2ModuleS_DSPAA 0301001505050 ain 350 ato ado Fig. 5.30: Auto correlation output for a voiced speech segment sa ie 803005000580 a OO Fig. 5.31: Auto correlation output for a unvoiced speech segment 5.14, An Image Processing System: + In comparison with the ECG or speech signal considered so far, image has entirely different requirements. Image is a two-dimensional signal and can be a color image or Gray image. A color image requires 3 matrices to be maintained for three primary colors such as red, green and blue, * A Gray image requires only one matrix, maintaining the Gray information of each pixel (picture cell or picture element), Dr. N Ajay Kumar, Sai Vidya Institute of Technology 3ModuleS_DSPAA ‘+ Image is a signal with large amount of data. ‘* Of the many processing, enhancement, restoration, etc., image compression is one important processing because of the large amount of data in image. + To reduce the storage requirement and also to reduce the time and band width required to transmit the image, it has to be compressed. ‘+ Data compression of the order of factor 50 is sometimes preferred. JPEG, a standard for image compression employs lossy compression technique. + Itis based on diserete cosine transform (DCT). © Transform domain compression separates the image signal into low frequency components and high frequency components. © Low frequency components are retained because they represent major variations, * High frequency components are ignored because they represent minute variations and our eye is not sensitive to minute variations. ‘+ Image is divided into blocks of 8 x 8, DCT is applied to each block. ‘© Low frequency coefficients are of higher value and hence they are retained, © The amount of high frequency components to be retained is decided by the desirable quality of reconstructed image. * Forward DCT is given by equation (2). 1 Te (Qx+Iun Qy+ In (2) ta= rap ee BE cos A cos Ot © Sins the coefficient’s values may vary witha large range, they are quantized. * As already noted, low frequency coefficients are significant and high frequency coefficients are insignificant, they are allotted varying number of bits. * Significant coefficients are quantized precisely, with more bits and insignificant coefficients are quantized coarsely, with fewer bits. ‘+ Toachieve this, a quantization table as shown in fig. 5.33 is employed. + The contents of Quantization Table indicate the step size for quantization. * An entry as smaller value implies smaller step size, leading to more bits for the coefficients and vice versa, + The quantized coefficients are coded using Huffman coding, it is @ variable length coding Huffman Encoding. ‘© Shorter codes are allotted for frequently occurring long sequence of I's & 0's, + Decoding requires Huffman table and dequantization table, ‘+ Inverse DCT is taken employing equation (3). The data blocks so obtained are combined to form complete image. Lely 2 Gre = FOOD cverfizy cos AME ogg EDR t=O 56 16 16 The signal flow graph for an 8-point DCT algorithm is shown in figure 5.33 Dr. N Ajay Kumar, Sai Vidya Institute of Technologyz 34ModuleS_DSPAA Fig. 5.32: Signal flow graph for an 8-point DCT algorithm ‘* The schematic of encoding and decoding is shown in fig. 5.34 16 11 10 16 24 40 51 61 2121419 26 58 60 55 14°13 16 24 40 57 69 56 “7 2s BF BO 18 22 37 56 68 109 103 77 2435 55 G4 a1 104 113 92 49 64 78 87 103 121 120 101 72 92 95 98 112 100 103 99 Fig, 5.33: Matrix used for quantization & dequantization Bx B block Fig. 5.34b: JPEG Decoder Dr. NAjay Kumar, Sai Vidya Institute offechnology 35ModuleS_DSPAA Note: Refer the images for PCM2002 FORMAT 0: PCM2002/3003, DAC: 16Bit, MSB-First, Right Justified FORMAT 1: PCM2002/3003 DAC: 20-Bit, MSB-First, Right Justified Dr Ajay Kumar, Sai Vidya Institute of Technology 36