Datasheet

Sentaurus TCAD
Industry-Standard Process and Device Simulators

Overview Value of Sentaurus TCAD in Technology Development

Sentaurus is a suite of TCAD tools and Optimization
which simulates the fabrication, Semiconductor manufacturers face the challenge of developing process technologies
operation and reliability of within strict time and cost constraints. One key factor impacting development time
semiconductor devices. The Sentaurus and cost is the number of engineering wafers needed to complete the development
simulators use physical models of the new process. By simulating the process flow and device operation before any
to represent the wafer fabrication wafers are processed and during wafer-based process optimization, TCAD reduces
steps and device operation, thereby the number of engineering wafers, saving time and money. Morever, Sentaurus
allowing the exploration and TCAD simulations provide engineers with important insights on the behavior of
optimization of new semiconductor semiconductor devices which can lead to new device concepts.
devices.
Benefits
The Sentaurus TCAD tools work Reduces technology development time and cost
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seamlessly and can be combined into Supports fast prototyping, development, and optimization of a broad spectrum
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complete simulation flows in 2-D of semiconductor technologies with comprehensive physics-based process-
and 3-D. modeling capabilities
Provides insight into advanced physical phenomena through self-consistent
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Sentaurus TCAD supports silicon
multidimensional modeling capabilities, improving device design, yield, and reliability
and compound semiconductor
Provides full-flow 3-D process and device simulation flows, with advanced
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technologies, covering a broad range
structure generation, meshing and numerics
of semiconductor applications.

Key Applications: Sentaurus Process

Framework
Process
CMOS, FinFET
`` simulation
Sentaurus Topography
Memory (DRAM, NVM)
`` Sentaurus
Power Devices (Si, SiC, GaN)
`` Workbench

RF Devices (GaAs, InP, GaN)

`` Structure
editing Sentaurus Structure Editor
Optoelectronics (CIS, Solar Cells,
`` Sentaurus
Photodetectors) Visual

BEoL Reliability
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Sentaurus Device Sentaurus
Device and PCM
interconnect Raphael Studio
simulation
Sentaurus Interconnect

Sentaurus TCAD Suite

Sentaurus Process diffusion, clustering, and interface Physical vapor deposition (PVD)
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trapping models to achieve an optimum Chemical vapor deposition (CVD)
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Silicon Process Simulator
trade-off between minimizing transient- Plasma-enhanced chemical vapor
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Sentaurus Process simulates the
enhanced diffusion and maximizing deposition (PECVD)
fabrication steps in silicon process
dopant activation. Spike and laser Low-pressure chemical vapor
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technologies in 2-D and 3-D. Equipped
annealing leads to nonequilibrium point deposition (LPCVD)
with a set of advanced process models,
defect–dopant pair concentrations and High-density plasma (HDP) deposition
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which include default parameters
dynamic clustering. To handle these Atmospheric pressure chemical vapor
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calibrated with data from equipment
process conditions, Sentaurus Process deposition (APCVD)
vendors, Sentaurus Process provides
includes a five-stream diffusion model Spin coating and reflow
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a predictive framework to simulate a
as well as models for {311} defects, Etching processes that can be simulated
broad spectrum of technologies, ranging
small interstitial clusters (SMICs), in Sentaurus Topography include:
from nanoscale CMOS to high-voltage
dopant-defect clusters, and transient
power devices. Wet etch
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dopant activation. With process-
With Sentaurus Process, users can Hemispherical etch
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induced stress being a key technique
easily simulate process modules and Reactive ion etch (RIE)
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for enhancing device performance,
integrate them into complete front Ion-enhanced etch
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Sentaurus Process computes all major
end of line (FEoL) process flows. An Ion milling
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sources of mechanical stress derived
advanced set of oxidation, diffusion, High-density plasma (HDP) etching
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from volumetric changes, thermal and
implantation, and mechanics models, Chemical-mechanical polishing (CMP)
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lattice mismatches, and deposited thin
combined with robust mesh generation
films. The complete stress history during
and structure-editing capabilities, cover
processing can be simulated and the
important process modules such as
resulting stress field can be seamlessly
ultrashallow junction formation, high-k/
exported to Sentaurus Device for
metal gate, and strained silicon.
evaluating its effect on electrical
A choice of advanced implantation performance. A model interface
and diffusion models are available in language allows the prototyping and
Sentaurus Process. Analytic implant implementation of new models to
tables cover an extensive energy range, keep pace with rapid technological
from sub-keV to several MeV. Efficient innovation. With this versatile tool, Trench deposition simulatedion in
and accurate Monte Carlo implantation new diffusion, clustering, silicidation, Sentaurus Topograph
models handle conditions not well and oxidation models can be readily
covered by the analytic models such as implemented. In addition, the interface between
sidewall doping of narrow trenches. Sentaurus Topography and Sentaurus
Sentaurus Process also offers a kinetic
Monte Carlo (KMC) simulator for Process allows users to combine front

atomistic simulations of the interactions end thermal and topography simulations

of dopants with point defects and in one environment.

extended defects in silicon.

Sentaurus Structure Editor
Sentaurus Topography Device Editor

Physical Topography Simulator Sentaurus Structure Editor is a 2-D/3-D

Sentaurus Topography simulates device editor which builds and edits

topography modifying process steps device structures using geometric

SRAM Cell simulated in Sentaurus operations. Sentaurus Structure Editor
Process such as deposition, etching, spin-on-
glass, reflow, and chemical-mechanical is powered by the ACIS® geometry

polishing in 2-D and 3-D. kernel, which is well proven and widely
In ultrashallow junction processing,
used in many CAD applications.
the continual reduction in thermal Sentaurus Topography includes models
budgets demands increasingly complex for the following deposition processes:

Sentaurus TCAD 2
The graphical user interface (GUI) of The script files of Sentaurus Structure AC, transient and harmonic balance
Sentaurus Structure Editor features a Editor use a LISP-like programming analysis. Flexible multidimensional
command-line window in which script language called Scheme. Scripting meshing engines allow users to
commands corresponding to the makes it easy to create parametric generate structured or unstructured
GUI operations are displayed. Script structures using simple variables or meshes effectively.
commands can also be entered directly variables defined as functions of other Sentaurus Device optional modules
at the command-line window. Doping variables, conditional constructs such allow for flexibility in configuring
profiles and meshing strategies can as ‘if’ or ‘do while’ blocks, and loops. application-specific solutions.
be defined interactively. The meshing
Sentaurus Device Sentaurus Device includes models
tools, part of Sentaurus Process and
for simulating state-of-the-art logic
Sentaurus Device, can be called from Silicon and Compound
and memory devices, including
the Sentaurus Structure Editor GUI and Semiconductor Device Simulator
physical effects such as stress- and
the generated mesh and doping profiles Sentaurus Device simulates the
orientation-dependent mobility, nonlocal
can be automatically visualized in electrical, thermal, and optical
tunneling, high-k dielectric mobility
Sentaurus Structure Editor. characteristics of silicon and compound
degradation, spatial quantization, and
All interactive operations are recorded semiconductor devices in 2-D and 3-D.
process-induced variability. Very-small
and a journal file can be saved, enabling Sentaurus Device supports the design
transistors requiring the solution of the
users to reconstruct device geometries and optimization of current and future
Boltzmann transport equation (BTE) can
by rerunning the journaled script file. semiconductor technologies including
be simulated with a PDE-based solution
nanoscale CMOS, FinFET, thin film
2-D and 3-D device models are of the BTE, the so-called spherical
transistors (TFTs), flash memory, SiGe
created geometrically using 2-D or 3-D harmonic expansion method, or with
heterojunction bipolar transistors (HBTs),
primitives such as rectangles, polygons, Monte Carlo methods.
large-scale power devices, compound
cuboids, cylinders, and spheres. The impact of radiation on semiconductor
semiconductors, CMOS image sensors,
3-D regions can also be created by device operation – single event upset
and solar cells.
extruding 2-D objects or sweeping (SEU), single event transient (SET), and
2-D objects along a path. Rounded total ionizing dose (TID) – can be also be
edges are generated by filleting, 3-D simulated with Sentaurus Device.
edge blending, and chamfering. The
A finite-difference time domain (FDTD)
way in which the overlap between new
solver is available to compute accurate
and existing objects is resolved can
optical generation profiles in structures
be explicitly selected, which allows
where the properties of electromagnetic
greater flexibility in structure generation.
waves must be taken into account.
Complex shapes are generated by
performing Boolean operations (union, The extreme operational conditions
subtract, intersect) between elements. common in power devices such
as secondary breakdown, multiple
snapbacks, floating guard rings, and
thermal runaway can be simulated with
Mesh and structure for NAND array
simulated in Sentaurus Device dynamically switched I–V curve tracing
and thermal effects.
In addition, Sentaurus Device enables Steady-state and transient transport
the analysis of complex integrated under high-voltage, high-current,
circuit phenomena such as and nonisothermal conditions can be
electrostatic discharge, latch-up, simulated with the numeric device
and single event upset. embedded with compact models using
CMOS Image Sensor structure created in Sentaurus Device incorporates an the mixed-mode capability.
Sentaurus Structure Editor
extensive set of physical models and
material parameters, and supports DC,

Sentaurus TCAD 3
 format (ITF) files. An alternative managing, executing, and analyzing TCAD
simulation flow allows the generation simulations. Its intuitive graphical user
of structures from mask (GDSII) and interface allows users to navigate and
interconnect technology format (ITF) files. automate the typical tasks associated
Raphael includes support for conformal with running TCAD simulations such as
dielectrics, trapezoidal conductors and managing the information flow, including
other advanced process effects. preprocessing of user input files,

Raphael can also extract resistance and parameterizing projects, setting up and

capacitance on structures generated executing tool instances, and visualizing

with Sentaurus Structure Editor and results with appropriate viewers.

Mesh and structure for LDMOS device Sentaurus Interconnect. With Sentaurus Workbench, users can
simulated in Sentaurus Device automatically generate design-of-
Sentaurus Interconnect experiments splits and can distribute
Sentaurus Device has an extensive set Back-End-of-Line Reliabilty Simulator simulation jobs across a computer network.
of models and parameters to support Sentaurus Interconnect simulates
compound semiconductor device physical phenomena concerned with Sentaurus Visual
development, including spatially varying back-end-of-line (BEoL) reliability. It TCAD Visualization
mole fractions, heterointerfaces, bulk comprises capabilities for simulating Sentaurus Visual provides users with
and surface trapping, polarization effects delamination, crack propagation a state-of-the-art interactive 1-D,
in GaN, anisotropic effects in SiC, and and other reliability issues related 2-D, and 3-D visualization and data
spatial quantization in 2-D electron gases. to mechanical stress, Joule heating, exploration environment. Sentaurus Visual
In addition, proprietary models can be electromigration and stress migration. supports TCL scripting, enabling the
implemented with a flexible physical postprocessing of output data to generate
model interface (PMI). new curves and extracted parameters.

Small-signal scattering parameters

Sentaurus PCM Studio
also can be simulated as a function
of frequency, leading to the extraction Process Compact Models
of important figures-of-merit such as The Sentaurus PCM Studio provides
maximum frequency of oscillation (fmax) a powerful environment for capturing
and unity gain cutoff frequency (ft). multivariate process–device
relationships using process compact
Raphael models (PCMs), allowing a fast

Resistance and Capacitance Field Solver turnaround for identifying and analyzing

Raphael is a gold-standard field TSV stress simulated in Sentaurus factors that cause parametric yield loss
Interconnect
solver for resistance and capacitance in manufacturing. PCMs are derived

extraction, designed to simulate the from systematic TCAD simulations,

Sentaurus Interconnect is designed and encapsulate relationships
electrical and thermal effects of today’s
specifically for semiconductor between process variations and
complex on-chip interconnect. Through
applications, featuring an easy-to-use device performance through a set of
Raphael’s easy-to-use graphical user
GDSII interface, full stress history, support analytic functions.
interface (GUI), process technology
for common BEoL semiconductor
data are entered and the interconnect For more information about Sentaurus
materials and global-local submodeling to
structures are automatically generated products and other Synopsys TCAD
support chip-packaging interactions (CPI).
and characterized for capacitance. products and services, go to

An alternative simulation flow allows Sentaurus Workbench [Link], contact your

the generation of structures from mask local Synopsys representative, or

TCAD Framework
(GDSII) and interconnect technology email tcad_team@[Link].
Sentaurus Workbench is a complete
graphical environment for creating,

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