igital Technigues (313K ike XII Observation: Sheep e oosee . es Dye payne Rp Mes AS ob Ser. COMMNLGHONS.....88 [Link].... ke oltage che ae kh Input De Output Qin Logic Output Volt: 0) oN) 0 @V) 716Y) [Rey KV Result(s) XVII Note: Below uiven are f more suchquestions so Can T flip flop be What is meaning ¢ Practical related questioiis Dilfereat Types of Tig Meatoned the IC no, ¢ few sample questions for reference. 1 a5 to ensure the used as fr tf Tosek ger used in D OCD Flip-Flop and Type of Mlip-flops and Draw its pin eon eacher must design ievement of identifies CO. faquency divider? Explain in 2 to 3 lines’Digital Techniques (313303) recommendation XVI Conclusion a1 Practical related questions Note: Below given are few sample-questions more suchquestions s0"a8 to, ensure the achie’ 1 State the operation 1: $1PO and PISO. 2 Draw obsfvation S for above operation. 3. Build circuit for SIPO., and PISO separately. 4 Draw giminig diagram f XVIL for-reference. Teacher must design ‘Maharashira State Board of Technical Education (K" scheme) 701Digital Techniques (313303) b) Actual circuit _ got 1B +Ae gs 6 Leo YY g20-A any-ag tase Y VII Resources Required S| Name of Resource ‘Supgested road Specification Quantity 1 Dicial Marimeter_| Digital Multimeter: 3/2 diit display. 2 > he Tests a wide range of Digital ICs such as : Digital IC Tester | 74 ceries, 445 Series af CMOS IC's. T [De power supply | #5 V Fined power supply i | Brealboant mx [7m i 5 [i THR6, ORT TEach [LED Red Yellow evlor 5 mut 1 TT Connecting wires | Single strand 0.6 mm Teilon coating As required [ET Revit TK 3308 As required IX. Precautions to be fallowed 1) Cheek IC beliore use 2) Set power supply to SV (Variable DC Power Supply) before connecting 3) Check all the connections as per cireuit diagram 7 Matornhiva Sie Boand of Technical Education (K™ seems) 7 n Cuvuswewed 44'S 6 UU x GQ © © c bo oe e . & © c & 6 6 7 ¢ 4 < ™ 3 3 3 3 - - v r v . 7 ? 7 pdfDigital Techniques (413303) x Procedure Test the IC using Digital Mount the 1C onthe breadboard ant Make the connection a per figure 63. “sv to +Vee pin of IC and GND pin to ground (on or off) for each combination of input as per truth table C tester Connect the Verity the truth table Repeat the procedure for figure 64 I 3 4. Observe the LED 8, 6. XI Resources Used Suggested! Broad Specification 37 dig 414 Mes Hage eos, 1432 Ve | ae | Nameof Resource + ee {cigital emuifime le “i tre -lostoxe 7 “re [4 [veo Reo XIE Actual Procedure Abe..T sigs Colo Sunn Ly XIE Observation: ‘Table 6.1: Observation Table for Half Adder an] Garp Sa T ; | Ts L_ ery Tip sainge | Tae Level] Oat Bea ao | wavy | oovy oO | ov nT oO ov aay) | 16v) ‘ if sv o ov svi | mio y | 6v ° ov wm fun] oO | ov \ sv Niaharashira State Board ut Technical Pdwation CR soheneyDigital Techniques (313303) Observation Table for Full Adder _ [ee ee Inputs _ sum Output Logic Level Output voltage 4 8 s Logic Level voltage He ae | ca “a ~ | eoyy | oer) | 00v) 5 au 8 e oovy | oy |v ri sv a aon | tess) | Ov) 1 = a oe won | ew | © ov ; s ray | H0vy ‘Ov 7 Er] a v 1 | 00) | HSN 0 av ; = ey | tev 10) © To ; 7 7) | 1 | 1) Y [ou : XIV Result(s) Tepe .abseve. Cir Suk. XV Interpretation of results “ie. leuecn....Clbosu... “eine XVE Conclusion and recommendation M2... leans UA dthe..end..8 Adder Carcut XVI Practical re Note: Betow given al questions ample questions for reference. Teachers must design more such questions so as to ensure the achievement of identified CO. 1 State drawback of Half Adder circuit. 2. Draw halfadder using NAND gates only 3. Design Half Adder using K-map. 4. Dray Full adder circuit using Half adder circuits rea fe Saluarashiea State Board of Technical Education CR" scheme? 4 SVVBRRVRUVEREEVEKOKC VE CVE CUVEE OULU OEDigital Leclutiques V13304) wv vt Practical No 7: Iplement 2 input, 3 input Subtractor Cireu Practictt Significance Subtractor is used in sp tems Where subtraction operations are required, such as in arithmetic unite of microprocessors, calculators, digital signal processing cireuits. and other d systems where subtraction is needed. Industry/Employer Expected Outcomess) Students will be able to test the fimetionality of the digital circuits/system Course Level Learning Outcome(s) Develop combinational logic circuits for given applications Laboratory Learning Outeome(s): 1. Verify the aruth table of Half and Full subtractor using Roolean expressions. Relevant Affective Domain related outeome(s) Identily PIN configuration of 1C. Handle the components and equipment carefully. Tollavw all safety precautions. Relevant Theoretical Background a combinational cireuit used in two single-bit binary numbers. lt has Wo inputs - minuend (A) and subtrahend (1) ~ and two outputs - the difference (D) and the Borrow (B).It is made of EX-OR gate, NOT gute (Inverter). and AND gate. The B output is | only when the subtrahend (1) is greater than the minuend (A). Difference Inputs HAs Outputs SUBTRACTOR Borrow 7.1: Mock diagram of Half subtractor Full subtractor is a combinational circuit that performs subtraction of two bits, ene is minuend and other is subtrahend. {n full subtractor “1” is borrowed by the previous adjacent lower minuend bit. Hence these three bits are considered at the input of a full subtractor. ‘There are two outputs that are DIFFERENCE (1D) and BORROW ( Bo). Vhtarnives Sine Doardof Technical Fuucation CR scheme)Dutiat Techniques (13303) A Difference (D) ‘Outputs (Bg) Fig 7.2: Block diagram of Foll subtractor Borrow VU Cireuit diagram a) muple circuit 4 : 328 Drererce = Ag — LED SZ 280 goraw od 2 ere ane ev Je 701 ~ Fig 7.3:1lalf subtractor Circuit Diagram ACER -Aeac. tee Vig 74: Full subtrictor Cireuit Diagram Maharashira State Boynd of Pevlinical Educate chemey 2Davita) Techniques (HITON bp Actual circuit aap T . ore e VW gine? VIL Resources Required T ‘ Suggested Broad Specification | Quant | CSVCGECCCCVCOC OG OCCVITITOCCVI TVS [Digital S e731 2 aligitdis 2 1 Fests a wide galat IC's such as 1 74 Series, 1045 Series of CMOS IC's, ; ined power supply t ? a =a t FANG, TANS, 7408, 7432 e oy nw color 3 ni ~ a Ff eonnecting wires | Single sind 0 6 ann Teflon coating {As requ ‘3 8] Resistor _ [Karson [AS required “9 Ix 5 to he followed! 4, 1 Cheek IC befare use > 2) Set power supply to SV (Variable DC Power Supply) hefore connectis ‘9 3) Chech all the connections as per eircuit diagram P Viaharashea Save Board ov Fechnwal Eaneaon TR scheme) a e{gta Techniques 4313303) XN Procedure 1. Test the IC using Digital IC tester 2. Mount the IC on the breadboard : 3. Make the connection as per figure 7.3, 4. Connect the +SV to +Vce pin of [C and GND pin to ground | 5. Observe the LED (on oF off) for each combination of input as per truth table 6. Verify the truth table 7. Repeat the procedure for figuee.7.4. XI Resources Used Sr Nami of Resource Suggested Broad Specification | Quantity No. T | igital muttimeiey| 3% cligit | P| Te sestey 4 series | 3 Xe tage Wey | 4] rresistor | Lien | XI Actual Procedure Tess... cnS.. hs, SABI, AAA, XII Observation: Aainve Table 7.1: Observation Table For Half Su igphal, AS [Link],.. ee Inputs Output Difference Borrow aloo . Logie Lovet | CMM T Logic Levet | Outet i) nee voltage Low (iy a av) | wavy | i 7 at! oN) | navy v 2 Hs) | Oy) 7 = 4 ony MSN) Liew | o | ov 5 ° ‘VIaharashara State Boord of Techinical Edueaiion (R° scheme 5 en en a”Digital Tevhnigues (315308) ‘Table 7.2; Observation Table For Full Subtractor { Taputs Output Difference Torraw Qu A B C | Logic Level _ Logic Level met aay @) (1) tr ocowy | ov) | OVD ov oO ov wor) | oy | 180 ee 1 SV oon | tev) | 90%) 1 5V ‘ sv | aory | te) | 16 | ov. ’ {sv navy | GON). | OV) ' Sv © AC Ov tay) | oow | 1a | oo ov o ov ayy [aes | oan | 0. ov 6 wv 1_| 1) | SY) 7 Bvt st [Sv XIV Result(s) “Substractew....ciclel XV Interpretation of results I Substrctom.c I related questions 2 Below given areu few sample questions for reference, Texchers must juns so ay to envure the achievement of identified CO, XVEL Pra Nan design more such ques 1. Draw hatf subtractor using NAND gates onty 2. Design Halt’ subtractor using K-mup. 3. Draw a full subtractor using half subtractor circuits Viiharishita Sisie Uinaadot Technical Pducniion (Rhema) WDicital Yechniques (11301) [Space for Answers]Disitat Technigues (313303) Gre vec —[oinnane [Description |... ssi} t D.C,BA BCD inputs uatlo Ontpnts ‘ tp 130) 8 jaee w2hb iF pamp Test wpe Far Ripple Dlanking Inpat tol}d a Blanking Input ste BO Ripple Blanking Ontpat Fig. 8.4 1C 7497 pin diagram IC 7448(BCD to 7-Segment decoder IC) IC 7448 is BCD to 7-Segment decoder IC whose output is active high depending on the corresponding DCD inputs so it is uscd to drive common cathode 7 Fig. 8.8 1 7448 pin di PDAS WWVS Owe Owe wweoEreee OO LL LL Waar a egiyaoe eS eee Digital Techniques (313303) VIE Circuit diagram 2) Sample Circuit 4,5 should he connected! tu Ingle 1Ver number 3, 20015/10/rcd-to-7-segment-decoderdriver) For normal functioning of IC T447 Pin Courtesy: (htps/[Link] con’ Fig 8.6: Circuit Dingram b) Actual circuit ell 56 (vee e Up «JF ct C3 wills ai reel 3 La wer OF pb o [fé nthe am wld ano C9 ae Visharahies Slate Boned of Fechnical Education CR" schemehVIL Resources Required Sr. gested Broad Specific: ion Quantity Name of Resource i F712 digit display r T | Digital Multimeter Tratar uttimetee 312 indisplay 7 of Digital FOS such as 1 of CMOS IC's. Tests a wide rat > | Digital C Tester | 44 caries, 40-45 Sevies ower SUPPLY nn 1 DC power supply Breadboard sj ic 3 Common anode | ye XD SOTILT S42 ' Teg Display | Common cathode ICLT 53 Teseg Display As required As required | ‘Single strand 0.6 qnm Teilon coating | TKS 33082 3] Connecting wires 9 | Resistor 1) Check IC before use. 3) Sex power supply 10 SV (Variable DC Power Supply) before connecting. 3) Cheek all the connections as per circuit diagram X Procedure 1. Testthe IC using Di IC tester Make the connection as per fig 8.6 3. Connect different BCD inputs from 0000 to 1001 and note down the corresponding output on the display . 4. Observe the outputs on a 7- segment display. Connect the +SV_ to + Vcc pin of IC and GND pin to ground 6. Observe the LED (on or off) for cach combination of input as per truth table 7. Verify the uth table NE Resources Used Name of Resource " | Suazested Broad Specification | Quantity _ 2 dig + dispia Th come Aw aios Tang Samra Sie Brandl Technical E— » > ’ » > > > , » » , > > » IX Precautions to be followed > ? ’ > > > » » , » » » > ® 5 ° ® ® ° ® .ee Se See Se SOUT ee eee Digital Technigues (313103) XI Actual Procedure be... TC...Us ing esdeac..... NIT Observation: ‘Table 8.1: Observation Table common anode display Display T Segment Coded Output BCD Inpus | plLe[HiAja b € a e t z output o| oj} ojo] o 0 0 0 0 0 | 1 a i » o 0 o t t 0 0 1 t 1 1 a toate toe afirfoe]o \loa]oa | \ Vio Jo “te olaletileo|t li lole feo fo fg aofafayopy o}|o le o 10 Jo fe. ofrfau}lrpo rao ° \ ty ( * XIV Result(s) “She ouipul oF segment. deemy. Tiahorsshiva State Gand of Technical Edusatiom (R" schereh a= sa relUG CUD PeVNVVWVWV wee eevee eeeuvevuwvevV You Digital Techniques (313300) tp Common Cathode Display (CCD): ning Caunmon eathode has all the cathodes of the 7-segments connected directly together to ground On, Cam Chaie 0).The individual segments are illuminated by application of high (Logicl) signal to coals idual anode terminals. For common cathode LED displays the (Cs are IC 7448, 1¢ 74248 7449 ete. are used, > vo «© 4 © £ a 4 JLULLLLLEL comwon CATHODE Fig. 8.2 Common Cathode Display (CCD) Common Anode Display (CAD): Common anode has all the anodes of the 7-segments connected together to VCC (Logic 1).The individual sezments are illuminated by connecting the individual cathode terminals to low (LogicO) signals to the individual cathode terminals. For common snode LID displays the ICs are IC 7446, IC 74246, IC 7447 etc. are used. COMMON ‘ANODE Pov ta bY bY oe ww bw 3 ap z- 8.3 Common Anode Display (CAD) Courtesy:(htips://[Link] om questions! 16858 leds Jifference-betw een-common. ind-common-cathode) IC 7447(BCD to 7-Segment decoder 1C) IC 7447 is BCD to 7-Segment decoder {C whose output is active low depending on the corresponding BCD inputs so itis used to drive common anode 7-seement dis “— ays. Maharashtra State Board of Technical Education (7K scheme)Digital Techniques (313303) ML Vv VI “Tirana Sa a Tea me) 7 Practical No.8: Test the output of BCD 10 7 Sazment Decoder using Digital 1¢ fy.) Practical Sig ; a BCD is an abbreviation for binary-coded decimal. BCD is @ way of representing di, umbers in binary form, The IC takes a bit BCD input and converts iC ing sy corresponding 7-segment display outputs. I is used to display decimal numbers, j Industry/Employer Expected Outcome(s) 2 ~ , Students will be able totest the functionality of the digital circuits/system. ) Course Level Learning Outeome(s) ! Develop combinational lagi circuits for given applications. ) Laboratory Learning Outcome(s): ’ 1. Consteuet and test BCD to 7 segment using Digital IC. , Retevant Affective Domain retated outcome(s) , Identity PIN configuration of IC. ’ Hancle the components end equipment caretully. Fotlow all safety precautions. , » Relevant Theoretical Buckground A decoder is a combinational cireit that conneets the binary information from ‘1 inputie ® © a maximum of 2a unique output lines. The 1C7447 is a BCD to 7-sewment pair D cone ‘The 1C7117 tshes the Binary Coded Decimal (BCD| as the input and eutpus"* 5 Fe ee Fpet segment decoders an IC decoder that ean he used to a seven segment indicator. There are two types of 7 igital display 1. Comm™ D anode display (CAD) and [Link] eathole dspay (cep) i aoe sone er has ABO inputs and 7 output pins (ato g sezmen, ~ Bock decodes devo - > > a a BCD Be way OOP pte > —] Se c > 0. est 7. Segment Decoder [~* 4 Outputs ‘ > aa . 9 » Fig. 8.1 Be ‘ Da 7-Segment Decoder 2 ° heeww we www yr ewer wee we wwe eww wrwewerwwerwrewvwwwvwwvue Digitol Techmigues (313303) VII Resources Required Name of Resource Suggested Broad Specification Quantity T | Digital Multimeter _| Digital Multimeter: 3 172 digit display 7] Tests a wide range of Digital C's such as 2 | Digital IC Tester | 74 6 renee ae 1 3 | _DC power supply +5 V Fixed power supply 1 4 | Breadboard Sem X 17cm 1 | (s(t 7a85 T 6 | LED Red /Yellow color 5 mm 1 7] Connecting wires | Single strand 0.6 mm Teflon coating As required | S| Resistor TROVSIOR As required | IX Precautions to be Followed 1) Check IC before use 2). Set power supply to SV (Variable DC Power Supply) before connecting. 3) Check all the connections us per cireuit diagram X Procedure Test the IC using Digital IC tester Mount the IC on the breadboard Make the connection as per fig 9.2. Connect the +5V 10 +Vec pin of IC and GND pin to ground Observe the LED (on or off) for given combination of input as per truth table Verify the truth table Nt Resources Used Re Name af Resource | Suggested Broad Specification Quantity LT! | enultieeler |g va digit 1 2 [ro tester | NY sete c : te | ce a Len _| Red Tyettow carers 1 rresis tore Je Re 193 05 1 Actual Procedure est te ER ASHO roaunt.... the... E¢....60..the..byead board. Mak. 2... Ae... ConnegHon....08..... PE. AY. Grd Vfatorasiea State Hoard ot Vechnical tdocation (7h ssherney =d Digital Techniques (313303) vo —! DI D3 4 ¥ n [ (Ourpury Dan LPs MUX Del E (Enable i) Sm $2 $1 $0 Select Inputs Fig 10.1: Block diagram of ni 1 Mul (Curtesy:huips:'/[Link]’search?elient=firefox-b&bin Sd&tbm=ise Types of Multiplexer (MU: 1. 2:1 MUX (2 lines t0 | line) 2. 4:1 MUX (4 lines to 1 line) 3. 8:1 MUX (8 lines to 1 line) 4. 16:1 MUX (16 lines to I fine) List of (Cs which provides multiplexing | IC No. [Function ‘Output State | FAST | QusT2T MUX _[ Output same as Taput piven i TASB Quad 2:1 SUX Output is inverted input [ss Dual MUN Output same a input ] Dual 41 MUN | Output is inverted input ————————___ [RrMox Usoth cutputs available (ec [RMON | Output is inverted input Vor MUX Output is inverted fi input NN | Outputs invert i —_] TT complementary outpatay ——__ Notaeice Sit Board oF Fecal Esato PE ‘scTemey m8 oo Wa Vga ese yvVV eee ery reeDigital Techniques (313303) VIL Resources Required Name of Resource Suggested Broa Specification Quan lity T | Digital Multimeter | 3% digit display I Vor2 Tests a wile range of digital ICs such as 74 Digital [C Tester 40:45 series of CMOS IC's. ZV fixed power supply of Variable DC power supply (0-30) DC Power supply Sem X Vem ingle strand wires of 0.6 mm As per Requiremen TANS T7S150 Red Yellow color 5 mm LED AG tor Sele and One for outputs) Lines 8 [Resistor 2202/3309 IX Precautions to be followed 1) Check IC hefore use. 2) 3) Check all the connections as per circuit diagram, Procedure Test the IC usiny Digital IC tester Mount the IC on the breadboard fe the connection as per fig 10.3 Connect the +5V_ to 4Vce pin of IC and GND pin to ground 3. Observe the LED (on or off) for each combination of input Verify the truth table x Resources Used Name of Re ure Suggested Broad Specific Multi rne-Lo-n ; ayia digi Set power supply to SV (Variable DC Power Supply) before connecting, ay per truth table Qua tity i Baread board S+Scm Viters —— Te ae) 1 pre sist : — —SSe | 2 20S /330-2 XU ee cae Actual Procedure Tes dhe Re hog Te eBoy mount dhe. te a ste Hoied uf Technica Famcation Oh on scheme) ee —— ee ’Digital Lechmiques (301) XVI Practical related questions Note: I atin for reference. T design more stich questiony so ay to cnvere the cme 1. List the funetion of the Strobe (G) pin? 2. Listthe absokate mavisum ratings of 1C 74151 3. List the name of manufactuzers of ICS used for this practicals? 4. List the applications where MUX is used? [Space for Answers] uchers mist of identified CO. owe given aren few sample q DORerla.. Maki hy. @.. uckonoie ation, i \Bagechng,.evend BLN. CONTR a1 @ Suray: BB Torey Gineay. Cory O..[Link]Vv v MI ordevice whieh has single input nq bs Ader exer (or demux) is a elect le e output line depend. A demultiplexer (oF UN) Eine se connected [Link] one OUP Hine depending, P ‘and m number select lines. Ts an be considered a a single... vironic demullplener © ot lines i | an electronic dem ; d : A butt aly. used in Bootean fanetion kena, multiple-output switch : lexers are me decoder circuils. ifeance ‘acu 1 Signi oni cri Demultipl (8) ‘on red Ow Fae functionality of the digital circuits/system. Industey/Employer Expect Students will be able 10 test 2 Outcome(s) Course Level Learn’ in i Jrouits for given applications. Develop combinational logic ¢ Laboratory Learning Outcome(s): » r r r » » 1. Build‘Test function of DEMUX Digital 1C , - - » D> d > line to selected one output from mar outputs, Handle the component and equipment carefully, Follow all safety precaution Relevant Theoretical Background Demuttiptexer has only one pe input. Taenhiptene me and“n” number of outputs along with “m” number of and dnarbuesitover several ut the everse operation of multiplexer i. itrecivs ot toa single pole m lrthe selected ot é * ‘ i i aa poe multiple way switch as shown in anu line. Hence demultiplexer ise#! p, fernultiplexer. The relation be lnion between the ov the m output fi ture. The enable input will enable tt ines and m sclect lines is as given” b D The demultipleser perform: fe 7 " Ms 0p} Process to a ‘multiplesing process it performs “oO YY" operation. Ht has show in he ‘nls one input * sire viven bel ? andr numb Decimal Decoder. Day wna on Demliteser eon he outrus (YO. Yl Yale 8iveN SL, strobe emhe so be wed as a decoder sino" Pin issued for enabling DEMUX » » » » »MV Ve eS Be Digital Techniques (313303) Viaharashira Sure Board of Technical Education (K Sheme) This... dyr.2..OF... [Link]...PL el rate... Class. a Ut alociuent JREGTANY... SP PliccrtionDoge Teche EES Practical Nal¢: Bed aad tet the femetionalig of 21 83) Muttipleyen 1 Practical Sigeificaece In mes of the CkNEEON Queens ON SE
| erst supply (00V) oe) +} Bresdboard 5 1 < | [> © Connecting Wires AS per wr z Requirement fy. > Se 1 > 2 for Select] ep Lep eW/Vellow cote, : : | ReWVellow color Smiy Lines ind +4 for a Notgate —_ ou sa IX Precautions to be followet 1) Cheek 1C hetore use 21 Set power supply te SV (Variable pe Iy to Sriable DC Poser Sy pIY) before 3 ech al : PIN) before conrectinn Check all the OU» pet cincut dinar Connecting vi shea Site Doardor Declan nn RemyDixital Technigues (313303) x Procedure 1, Test the (C using Digital IC tester 2. Mount the 1C on the breadboard 3. Make the conneetion as per 4. Connect the +5V_ to + 5. Connect the Strobe PIN 16 to gro! 6 7. Verify the truth table NL Resourees Used c pin of IC and GND pin to ground und. Observe the LED (on or off) for each combination of input as per truth table Nanie of Resource Suggested Rroad Specification Quantity T Toigital rauttimeles| 112. digi {ese > | Te tester Ty seves ; 3 | Bread hood 5S cm XHCM ' 4 Ic Sn iss ' Actual Procedure NIL Observation: Table 11.1: Observation Table Inputs Outputs ‘Outputs (Volts) | Select Strobe | yy ] 3 t iG to | Yep Me] | Ya] Ye | ve Ys x] X 1 x © |o |o |e | 6 jov [ev lov ov) | _o avy 0 1 1° fo [9 (A lov lo fow lov ov) | 16%) 0 1 9 }o0 lo fo levi |o [ov ov) o | 1 9 fo 1/o | 9 [ov lov jov jo 16v) | 0 1 CT° To (6 Jov[ [OV [ov | (Write the observ (Note: * ation with respeet to Inputs} indicates the don’t care condition. It means the status of selected input may be any combination) ‘Maharashira State Dard of Technical Edacaion (°K seheme) 74Digital Techniques 31301) REO. PIAY,...Cb... CREO... OVE, LO BL RCI. Ge CLIC AS. 2A CGT © U iProG).t..... 2. OY ATM EN Ae ore AEDS. CHOY. RCM sot 2. cheat Sh ABMAING..). Qala ranagmen | @ oresance. “.[Link]: » Incoreasecd....[Link] @. mead... Communication. GQ). Porm... LACH OOo References/Suggestions for further reading 1. hups:/[Link] com/datasheets/parts/datasheet/477/SN74155-paf. php 2. hutpsvsvww, [Link] watch?v=3aWLCHY_EPA (NPTEL Video Link on Demutiptever) XIX Assessment Scheme Performance a ] Indicators {_ Weeeere | || Process Related : 1S Marks I 60 % | 1] Handling of the components 1 10% [2 | ientification of components | 20% | 3 | Measuring value using suitable instrument i 30% 4) working inteams I WP. Product Related: 10 Marks I 40% 5] Calculated theoretical values of given component 10% | CA 6 | Interpretation af result 7] Conclusion 8 | Practical related que: 9 | Submitting ions journal in time Total (25 Marks) Marks Obtained | Process related | Product related Total (sy (0) (25) | Viaharashira Stats Dard of Technial anata NRE 7WIWVWWVW Vw weve wvvwwwwwwwwwuwve Mga! Techmgury (HANLD R eo < 8 Qo 1 8 0 7) Sameas) Same) a ® 7 Rew | Rae | Lprevinns previnws ei. eT y 0 tio | t?eye., Cryer. . ToD Names Name as Tt | Rae) Raw “| _ | LEITH es Fig 12.2 Trath eatiie for Ore etiagram tn Pag UU aD wu Circuit diagram a) Sample circuit cin Ss Fig 12.3 SR Flip-Flop using NAND gates by Actual circuit Seen ee —y of \ ; : . si] Sy } a a0 | ’ Hees ' ! ' \ ' ' —— Ww , t ay 5 * a, 5 L n ‘4 femme i se eeee - Y Y § Mharashing State Hoard ot fectaical Eatication OK” seheaey ee nNal Tech VIN Resources Required eee fication Quantin, )! ’ sore | oe ~|' ues (313303) Suggest Brod SUSE si i Teaigit di _ Re Fests a wide eane® or aigital IC’ > | pigtal IC Tester is, 48 seo! 108 IC : cts maiableDC |) FSV fixed power supply or Variable ry De Power supply yawer supply e0-30¥2 {ot iS Sem X Vem a i AS per ' Conne single strand wires of 0.6 mM wegen Wo 6 \Ic 7400 ft | 7 IRed/Vellow color 3 mm | ; 1 TED. 2 | Resistor pz0613300 4 1X | Precautions to be followetl Ly Check IC before use, ' 3) Set power supply 10 SV (Variable DC Power Supply) before connecting. 3) Check all the connections as per eiret diagram ' xX Procedure 1. Mount the 1C7400 onthe breadboard : 2. Make the connections as shown in figure 12.3 3. Apply the supply voltage tol +5V. 4. Apply inputs according to the ebservation table. ' 5. Observe the LED (on oro) for each combination of input as per truth table 6. Verify the truth table. , XL Resources Used! y [* Name af Resource 5 i) < Suggested Broad Specification Quantity | | A _|mmuitin e4 err | ava digit distiay | \) “4 00 Ta REO iyerrows a Is NIL Actual Procedure a ‘ Y , Wott ake ae eee ~ S.A. 2... Baie Con . the... aes, Waarashia Site Bordwvyuvvuwvwewewe ewe ewe wee wee weer ewe eee eee eeu we wv J Toghagoes (UROL A. Aeely the. ase 2M, GANG Sows Jahte. RUT Otvervation: Vutite [Link] Observation Table for SIC EMP Eloy wen OU ; o | Poi | Ontpar | Cogle Putpwt | ptemark i Votiage Level | Valtage | W) (ony _W) [own | I ow ft Su ne ev Ce Sev 1 au Tray [reve 1 av 0 av Tew ney - oS ov 7 XV Interpretation of results NOY... SAR Pe&uious.... UP. Gs Js 00... Set 6Pb, 2D. J mestd be cerey anid ve XVE Co Ws... Aveid,...ac8.68...Conel ion. APE Geo Od. Change. NV Pra Nate: Hetow given are few nee. Teacher must dexign more suclquestions 99 ay fe af itentifies CO, {Why the Name of Elip-Plap is gleen SRE Lip-f lop’? tion bv SR Plipel lop? al related questions Esplin the Roce List how race condition can be resolved? State application of SR Flip-Flop? Watarishira Safe Noun of echnical Falveation PR sehiemey mDigital Techniques (313303) AIM 2.6... Sv. 4, ne havi ts 3 Mularashtta State Board of Techuicil Edagation OR homey LWW e ye bey eevee uEsDia Peshnigues O70 behavior. counters duc to their togeling In summary, The D Mip-ttop stores data and updates its ousput on clock transitions, while the 1 Mip-flop toggles its output based on elock transitions and the state of ils toggle Input. Both are essential components in digital cireuit design, offering versatility and functionality in various applications, [Topar [Output | b Quod 0 0 1 1 Output Qutt @ Figure 14.2 a) T FF using 7476 b) Symbol c) Truth Table VIL Circuit diagram a) Sample circuit Figure 14.3 Sharing te Board of Technical Education (7B seheme) aaDigital Techniques (313303) Figure 14.4 T FF ws seca vb) Actual circuit Pa j= ics af ve PR GINO] yg 370-0 * [is Ay Pp 70% a es a a setuts 2 k @ Et Tig wed Tinta NEC TR ie tate Coes, eren 4 ti. i ¥ DID Ue YD LG ES CO Se re ‘weyDigital Tectniques (313303) ‘Output Qt Togie | Output Level |) Voltage (ory a) Observation: Tablet Output Qa Auput Gutput o Voltage w) OOV) oy 16) sv Int XVI Conelusinn and recommendation ‘nla. chonge. Cone lex, tn Result(s) ES. Vishoraatirs State Ward of Techical Custom Ch shemar Ond. case, f... Ce mova, Se. FEN, Practical related questions, ifian... VOW a nes. in... re Few sample questions fur ri inns for reference. Teacher must d mare suchqwestions s0 ay to ensure the achi ifeco. Cam Tip flop he used ay trea What is meaning of Toggle? Ditferent Types of 1 Fused in D amd Type oF Mip- tops Mentioned the (C m6. of D Flip-Flop and bore se ut ns @ Aoaany Lathe hievement of identifies CO, 9 divider? Lyptain in 2 to 3 fines? Pin configuration? asN NUNN NNN NWT WSN VWeewWweVeeSelUlverlClU eC elem el el erelUlel Perel etl erelh Trlr serlmlUmvTTClUCcrmlUcrcCUc CrmLUCTUrh UU Digital Teshguen (319103 [Space for Answers] ah. [Link]..clock... Puls @ the. TO LIOR. keg gles AS... CMHALL SER CAEN nA RHVRA Ag A @APRUL LES EAE AS ee ee ; : Co WAYS... Seas SMO OO. OF [Link] eee £108. - Higpcul Cimpeut & Commons US id... eo) AHO HE Pose. ~Amgg TE. “Ay negative. S07 TAM...Digital Techniques (313303) 1 vl Practical No.6: Implement 2 input, 3 input Adder Cireuit. Practical Significance In many computers and other kinds of p logic units (ALUs). They are also used in ot are used to calculate addresses, table indies and similar operations. he arithmetic rocessors, adders are ised int where they her parts of the processor herement and decrement operators Industry/Employer Expected Ovrcome(s) Students will be able to test the functionality of the digital circuits/system. Course Level Learning Outcome(s) Develop combinational logic cireuits for given applications. Learning Outcomes): Laborato the truth table of Half and Full adder 1. Ver 1 circuits for the given input. Relevant Affective Domain related outcome(s) Adentit PIN configuration of IC. Handle the components and equipment carefully. Follow all safety precautions. Relevant Theoretical Background A half adder is a digital logic cireuit that performs binary addition of two single-bit binary srumbers It has two inputs, A and B, and 160 outputs, SUMS) and CARRY (C). The SUM vat is the Teast significant bit (LSB) of the result, while the CARRY output is the most Significant bit (MSG) of the result, indicating whether there was @ e3FFy-oNet from the setion ofthe two inputs, The half adder ean be implemented using one EX-OR gate and one AND gate, The C output is | only when both inputs are 1. . A Sunt Inpiee Outputs a Camry Fig 6.1: Block Diagram of Half adder Te full adder iv a combinational circuit which is used to perform addition of three input bits. The fill adder adds the bits A and B and the carry trom the previous bits addition called the carry in (Cin) and the outputs the sim bit (S) and the earry bit called the carry wut (Cou) The tives the value of the least significant bit of the sum. The variable Cout gives the variab output earry. ‘Niharashira Stare Board of Fechaieal Education (°K scheme) 1 THANnAne nannnnn nn h 4 ! | nan PDD RRR RDN D DPD aVi b> gues (313303) ee A Sum (4) Inputs —9] Outputs c Carey (Cy Fig 6.2; Block Diagram of Full adder vit Cireuit diagram a) Sampleeireuit Fig 6.4: Full adder Circuit Diagram Shossh Stte Hand of Technical Education UR SeNeT6)Digital Techniques (313303) [Space fur Answers} Alunc:l tion. a HE CCL Viaharashira Slate Hoard of fechnical Education (-h schemey 0LWW ww Vee ew ewww ee we we HH Digital Techniques (113303) XVIL_ Practical retated questions = Neluw given are a few sample questions for reference. Teachers must f ions so ay to ensure the actievement of identified CO. 1. Draw logie circuit for | bit magnitude comparator also write its truth table 2. Draw pin diagram of IC 7485 also write its truth table. 4. List the name manufacture of IC 7485 & list any Four elect cal characteristics of it, [Space for Anewers} Se noic [Link]. nicaracdichian Vober Gad asics Motta ge... Voldage, Matiarashira Sinte Goand of Technical Pawcation Rv shee)vYVVVVVwewuwveeweweeveve we eee ee ee re Digs Tesbniques 313303) ebsere. the bh [Link]. 0260 .08..Pe ola hy cleus he ota. ete... nM emey.. XUL Observation: Table 10.1: Observation Table Inputs: Ourputy | Dit pute Strabe | Data Input Seleet Input elie vy ¥ G D, Sr os Sy £01 vato | (OP vot, 0 Tay | ony | vay | 1 LO ov 0 Deo avy] omy) | ey | VO _[-av o be voy | 1eyy | omy | 1 | o “fav o pop Loew | ren | ay [fo ov o ” Tavy | ov | owv) |! oO OM Tay |_oovy | tev | 1 6 ov [a6 Tey) | Oy) | ° OU Tew | bey | 13M [4 cm ou x x Xx 0 0 ow] (Write the observation with respect ta Inputs) (Note: °X" indicates the don’t eare condition. Ik neans the status of selected input may be combination) XIV Result(s) “aitigy “Anat “oukeuk \ ANOS | XV Interpretation of results ER ger ride. output) Ay eins lq’ Jews XVI Conclusina and recommendation DBE. earch At Suid. Hest. Stncction at SAS Anis ee eax ‘Charaira State nar of Fechnical Pdocanion R whemey wepre vee ee eee eee eee Digital Techniques (513303) aN : DEMULTIPLEXER Fig 11.1; Block diagram of 1: n Demultiptexer Curtesy: https:/ [Link]/w/fcontenvuploads/2022/09/demultiplexcr py, Types of Demultiplever (MEMUX): 22 MUX (I Tine to 2 fines) MUX (1 line to 4 lines) 3.8 MUX (1 Tine to 8 Lines} 4. 1:16 MUX (I Hine to 16 tines) vee 26 2G 2v3 2v2 2¥1 2yYo Fig 11.2 [C SN74155 1:4 Demi Courtesy: hups:/'[Link]/datasheets/parts/datasheet/477/SN74 [Link] VIE Circuit diagram a) Sample eireuit Fig 11.3 Cireuit Diagram of 1: 4 DEMUN using IC SN 74155 (Note: Ouiput of IC SN74155 is complementary to get desired output invert it by connecting NOT gate) Maharashtra State Hoard of Technical Education CK® scheme) 7Digital Techniques (313303) NIV Result(s) Practical related questions Note: Relow given are few sample questions for reference. Teacher must design more such questions sous to ensure the achievement of identifies CO. , 1. List the fianction uf Strobe (G) pin? List the name of manufacturers of IC’S used for this practical ? Draw the Circuit diagram for 1:8 DeMUX using IC SN 74155 and its truth table? 4 State how DEMUN have helped for (ata transfer in electronic circuits? [Space for Answers] WO. Bada. Natids ty @ Synchronizols an. BD. che eng evens OA... Cont gp) FO Supe y wolte.g ¢ .toews. Noting @” @. Output votaje os fst . Dine ut STE | SO oitveul tury, Maharasiira State Toad « ae Technical Eada DP“S"S"s-e se eowvrvewv eweu m Vv v MI Maharastra SoS Booed oF Poe 1 (313303) truth t Practical No,12: Implement and verify the Practical Significance loge cuit se Fr storing binary information, i aloo, mn bee at ene loite tates typically O (reset) and 1 fet Py itcan non ne bit memory. It has £80 stable states ty ( ea sn iseunent te vat dts amueted to change it by applying 2 cloc Pulls, Flint fundamental building blocks ia digi circuits and Data synchronization, Industry/Employer Expected Outcome(s) Students will be able to test the functional of the digital circuits/system, Course Level Learning Outcome(s) Develop sequential logie circuits using Flip-Flops, Laboratory Learning Outcome(s): 1 Builds unctionalyy of RS flip lop using NAND Gate. Relevant Affective Domain rels cil outeume(s) 'lip-Flop data heldine/storing abil Handle the component and equipment carefilly, Follow all safety precaution Relevant Theoretical Background Disica! citeuits have: many combinations combinational oF sequentil, The SutPU OF combinational cireui ‘inputs. In contrast, sequential cy uit deer ‘teuit depends not ont also upon the intemal ilies ta Ste OF the circuit. Basic bury Sequential circuit are the Nip-tlops (HFS), the Fry ene NMS Al Cerin interval oF tna Of logic circuits. they are classified as ete ts depends only on the cu Surrent value of the inpul tit si ® Blocks (memory elements) of 3 * ee Ts change their ouput state depending up 9 emronieed with some viocy. Pulse applied 10 it ame R R Fig 21a sp 8 "ch using Now fates Sintu m Vv Ml Drip Flop (eh Flip-Flop) x used to provide time delay, They are basis build ip -Flop (Delay FI of Shift Registers ‘ i “ aos wn Resi Flip-Flop) experiences a change in output in each clock edge ip-Flop (Toggle Mip-Flo vide lop can also be used to desi ' Hence it can be used as a lrequency divider, T Flip-Flop ie Cony Industry/Employer Expected Outcome(s) mC Students will beable 1 tes the functionality of the digital cireuits/system, , Course Level Learning Outcomels) ; Develop sequential log eireuts using Flip-Flops: Laboratory Learning Outcome(s): |. BuildTest functionality nd Truth Table of D and T flip Nop. ’ ' , , Rekvant Affective Domain retated outcome(s) , flare che componest and equipment carly. Follow all safety precaution , . d Relevant Theoretical Background [ifs ane fundamental bailing blacks in d The D and T fip-feps applications Lp ® single data input (D) and two Outputs: Q (the stored valu! the stored value) state (4 ony sh her lex, risin ils output iffe state to an © The D inputis s ‘eflects the si noth ‘tions foot D en the clock input (CLK) teansitions & * falling edyey hen thee arp ite of dnd stored yy ecu the D input Tas ee for sestt ‘B8 Storage, synchroniz fon, and edge dete" T Flip-hop (tp d °f2¢ Fip-Flap The [Link] has ne 9 Has a singe "PH OD) eatte led the ‘ qe ‘eale input, and two output Phased orang We “Nsition ef the clock input ccrxon if 1 AP Ut yatag me ® change " . POL its st . “EES its state) ay, wach etock tans Phan eajueng SMES OF tock ransitions. acont oT Tecin a = iil! 7 OM pulse generation, an HiDuptat Techntaues (114302) VIE Resources Required Sr No. T Name of Rexouree | Suggested Broad Specifieatis Digital Multimeter [5% ligit display Tests a wide range of digital 1C"s sucht ay 74 series, [iia IC Tester linia series of CMOS IC's EW fixed power supply of Variable DC power 3 [De Powersunnly Cypeiy (AsO) 40 | Breadboard Sem X Hem P As per 5 | Connecting Wires | nee strand wires of 6.6mm. Requi | 6 hie eae {we J { 7 | LED [ed Yell Yellow color $ mm 2 ry Raion Pam 0 2 IX Precautions ta he fallowed Cheek IC before use. Sct power supply to 3¥ (Variable BC Power Supply} before connectiny. 3. Check all the connections as per efreuit diagram: x ¥ Procedure Mowat the 1C776.0n the breadboard Make the connections as shown in Gyure 14.3 and 144 Apaly the supply vollage to 1 +5V. Apply inputs acconding to the ebservation table, Observe the LED (on ur of) for each combination of input as per truth table 6. Verify the uth table, XI Resources Used i | ) e Nameaf Resource Suggested [road Specificution — | Quantity 1 [Bigset rauitimeter | g/a_chgy + clisptay | us on | ? a) booed Ss fomu lien, | torn 4446 i V Redster 210 Ua | | MU te wh