Trimless

Voltage Controlled Amplifier

Data Sheet SSM2018
FEATURES FUNCTIONAL BLOCK DIAGRAM
117 dB dynamic range
SSM2018
0.006% typical THD+N (@ 1 kHz, unity gain) VC
140 dB gain range
No external trimming required
Differential inputs G VG
Complementary gain outputs
+IN
Buffered control port GAIN –IG
CORE
I–V converter on-chip –IN

TE
Low external parts count 1–G V1–G
Low cost
–I1–G

00345-001
Figure 1.

GENERAL DESCRIPTION
The SSM2018 represents the continuing evolution of the Frey
Operational Voltage Controlled Element (OVCE) topology that
permits flexibility in the design of high performance volume
control systems. The SSM2018 is laser trimmed for gain core
LE Additional features include differential inputs, a 140 dB (−100 dB
to +40 dB) gain range, and a high impedance control port. The
SSM2018 provides an internal current-to-voltage converter.
Thus, no external active components are required.
symmetry and offset. As a result, the SSM2018 is the first This device is offered in 16-lead, plastic DIP package and
professional audio quality VCA to offer trimless operation. guaranteed for operation over the extended industrial
SO
Due to careful gain core layout, the SSM2018 combines the low temperature range of −40°C to +85°C.
noise of Class AB topologies with the low distortion of Class A
circuits to offer an unprecedented level of sonic transparency.
B
O

Rev. C Document Feedback

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SSM2018 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Control Section ........................................................................... 11
Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 12
General Description ......................................................................... 1 Basic VCA Configuration ......................................................... 12
Revision History ............................................................................... 2 Proper Operating Mode for the SSM2018 .............................. 12
Specifications..................................................................................... 3 Output Drive ............................................................................... 13
Electrical Specifications ............................................................... 3 Upgrading SSM2018 Sockets .................................................... 13
Absolute Maximum Ratings ............................................................ 4 Temperature Compensation of the Gain Constant ............... 13
Transistor Count ........................................................................... 4 Digital Control of the Gain ....................................................... 14
Thermal Resistance ...................................................................... 4 Supply Considerations and Single-Supply Operation ........... 14

TE
ESD Caution .................................................................................. 4 Operational Voltage Controlled Element................................ 14
Pin Configuration and Function Descriptions ............................. 5 Voltage Controlled Panner ........................................................ 15
Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 16
Theory of Operation ...................................................................... 10 Ordering Guide .......................................................................... 16
Compensating the SSM2018 ..................................................... 10

REVISION HISTORY
2/13—Rev. B to Rev. C
Updated Format .................................................................. Universal
LE 7/02—Rev. A to Rev. B
Deleted references to SSM2118T........................................... Global
Reorganized Layout ............................................................ Universal Edits to Features ................................................................................1
Changed SSM2018T to SSM2018 ................................ Throughout Edits to General Description ...........................................................1
SO
Changes to Table 2 and Transistor Count Section ........................ 4 Deleted SSM2118T Functional Block Diagram ............................1
Added Table 4..................................................................................... 5 Deleted 16-Lewad Plastic DIP and SOL from
Changed Theory of Operation of the SSM2018T Section to Pin Configurations ............................................................................3
Theory of Operation Section; Changes to Figure 28 ..................10 Edits to Ordering Guide ...................................................................3
Changes to Control Section ...........................................................11 Deleted SSM2118T Typical Application Circuit ...........................3
Changed Applications Section to Applications Information Deleted TPCs ................................................................................ 7–8
Section, Changes to Basic VCA Configuration Section .............12 Edits to Applications ...................................................................... 10
Changes to Output Drive Section, Upgrading SSM2018 Sockets Deleted section Basic VCA Configuration For
B

Section, Temperature Compensation of the Gain Constant The SSM21218T ............................................................................. 11

Section, Figure 30, and Figure 31 ..................................................13
Changes to Digital Control of the Gain Section ..........................14
Updated Outline Dimensions ........................................................16
O

Changes to Ordering Guide ...........................................................16

Rev. C | Page 2 of 16
Data Sheet SSM2018

SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VS = ±15 V, AV = 0 dB, RL = 100 kΩ, f = 1 kHz, 0 dBu = 0.775 V rms, simple VCA application circuit with 18 kΩ resistors, −VIN floating,
and Class AB gain core bias (RB = 150 kΩ), −40°C < TA < +85°C, unless otherwise noted. Typical specifications apply at TA = 25°C.

Table 1.
Parameter Conditions Min Typ Max Max (E Grade) Unit
AUDIO PERFORMANCE
Noise VIN = GND, 20 kHz Bandwidth –95 –93 dBu
Headroom Clip Point = 1% THD + N 22 dBu
Total Harmonic Distortion plus Noise 2nd and 3rd Harmonics Only
(25°C to 85°C)
AV = 0 dB, VIN = +10 dBu 0.006 0.020 0.01 %

TE
AV = +20 dB, VIN = −10 dBu 0.013 0.03 0.02 %
AV = −20 dB, VIN = +10 dBu 0.013 0.03 0.02 %
INPUT AMPLIFIER
Bias Current VCM = 0 V 0.25 1 µA
Offset Voltage VCM = 0 V 1 15 mV
Offset Current VCM = 0 V 10 100 nA
Input Impedance
Common-Mode Range
Gain Bandwidth

Slew Rate
LE
VCA Configuration
VCP Configuration
4
±13
0.7
14
5
MΩ
V
MHz
MHz
V/µs
OUTPUT AMPLIFIER
Offset Voltage VIN = 0 V, VC = 4 V 1.0 15 mV
SO
Output Voltage Swing IOUT = 1.5 mA
Positive 10 13 V
Negative −10 −14 V
Minimum Load Resistance For Full Output Swing 9 kΩ
CONTROL PORT
Bias Current 0.36 1 µA
Input Impedance 1 MΩ
Gain Constant Device Powered in Socket > 60 sec −30 mV/dB
B

Gain Constant Temperature Coefficient −3500 ppm/°C

Control Feedthrough 0 dB to –40 dB Gain Range ±1 ±4 ±3 mV
Maximum Gain VC = −1.3 V 40 mV
Maximum Attenuation VC = 4 V 100 dB
O

POWER SUPPLIES
Supply Voltage Range ±5 ±18 V
Supply Current 11 15 mA
Power Supply Rejection Ratio 80 dB

Rev. C | Page 3 of 16
SSM2018 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TRANSISTOR COUNT
Table 2.
Parameter Rating Number of Transistors
Supply Voltage SSM2018 .........................................................................................125
Dual Supply ±18 V THERMAL RESISTANCE
Input Voltage ±VS
Operating Temperature Range −40°C to +85°C
θJA is specified for worst-case conditions, that is, θJA is specified
Storage Temperature −65°C to +150°C
for device in socket for P-DIP.
Junction Temperature (TJ) 150°C Table 3. Thermal Resistance
Lead Temperature (Soldering, 60 sec) 300°C Package Type θJA θJC Unit
ESD Ratings
16-Lead ,Plastic DIP 76 33 °C/W
883 (Human Body) Model 500 V

TE
EIAJ Model 100 V 50pF

18kΩ
VOUT
Stresses above those listed under Absolute Maximum Ratings 1 16 V–
may cause permanent damage to the device. This is a stress V+ 2 15
rating only; functional operation of the device at these or any 3 14
other conditions above those indicated in the operational 4 13
SSM2018T 150kΩ

maximum rating conditions for extended periods may affect

device reliability.
LE
section of this specification is not implied. Exposure to absolute
VIN+
VIN–
1µF
18kΩ

1µF 18kΩ
5

7
12

11

10 1µF
V+

1kΩ
3kΩ
VCONTROL

00345-003
8 9
47pF

Figure 2. Typical Application Circuit

ESD CAUTION
SO
B
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Rev. C | Page 4 of 16
Data Sheet SSM2018

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

+I1–G 1 16 V1–G
V+ 2 15 BAL
–IG 3 14 VG
–I1–G 4 SSM2018 13 GND
TOP VIEW
COMP 1 5 (Not to Scale) 12 MODE
+IN 6 11 VC

00345-002
–IN 7 10 V–
COMP 2 8 9 COMP 3

Figure 3.

Table 4. Pin Function Descriptions

Pin No. Name Description
1 +I1−G Positive Current Feedback Input for V1-G.

TE
2 V+ Positive Power Supply. Connect this pin directly to the positive power rail.
3 −IG Negative Current Feedback Input for VG.
4 −I1−G Negative Current Feedback Input for V1-G.
5 COMP1 Compensation Pin. Apply a capacitor to the COMPx pins according to the Compensating
the SSM2018 section.
6 +IN Non-Inverting Current Input.
7 −IN Inverting Current Input.
8

10
COMP2

COMP3

V−
LE
Compensation Pin. Apply a capacitor to the COMPx pins according to the Compensating
the SSM2018 section.
Compensation Pin. Apply a capacitor to the COMPx pins according to the Compensating
the SSM2018section.
Negative Power Supply. Connect this pin directly to negative power rail.
11 VC Control Voltage Input Port. Apply voltage to control VCA according to the Control Section.
12 MODE Operating Mode Pin. Selects Class A or Class AB operation as described in the Proper
SO
Operating Mode for the SSM2018 section.
13 GND Ground.
14 VG Output Voltage at Gain of G.
15 BAL Symmetry Trim Input for Older Version. Do not connect for SSM2108T operation.
16 V1−G Output Voltage at Gain of 1-G.
B
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Rev. C | Page 5 of 16
SSM2018 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0.1 1
TA = +25°C TA = +25°C
VS = ±15V VS = ±15V
RF = 18kΩ RF = 18kΩ

AV = +20dB
0.1

THD + N (%)
THD + N (%)

0.01
AV = –20dB

0.01
AV = 0dB

TE
0.001 0.001

00345-007
00345-004
20 100 1k 10k 20k 10m 0.1 1 2
FREQUENCY (Hz) AMPLITUDE (VRMS)

Figure 4. THD + N Frequency (80 kHz Low-Pass Filter, for Figure 7. THD + N vs. Amplitude (Gain = +20 dB, fIN =1 kHz,
AV = 0 dB, VIN = 3 V rms; for AV = +20 dB, VIN = 0.3 V rms; for AV = −20 dB, 80 kHz Low-Pass Filter)
VIN = 3 V rms)

100 1

90

80

70
TA = +25°C
AV = 0dB
300 UNITS
VIN = 10dBu
VS = ±15V
LE THD + N (%)

0.1
TA = +25°C
VS = ±15V
RF = 18kΩ

60
UNITS

50
SO
40
0.01
30

20

10
0.001

00345-008
0
00345-005

–60 –40 –20 0 20 40

0 0.005 0.010 0.015 0.020 0.025
GAIN (dB)
DISTORTION (%)
B

Figure 5. Distortion Distribution Figure 8. THD + N vs. Gain (fIN = 1 kHz; for –60 dB ≤ AV ≤ –20 dB, VIN = 10 V
rms; for 0 dB ≤ AV ≤ +20 dB, VIN = 1 V rms)

1 0.1
TA = +25°C TA = +25°C
RF = 18kΩ
O

VS = ±15V
RF = 18kΩ

0.1
THD + N (%)

THD + N (%)

0.01

0.01

0.001 0.001
00345-006

00345-009

0.1 1 10 20 5 6 9 12 15 18
AMPLITUDE (VRMS) SUPPLY VOLTAGE (±V)

Figure 6. THD + N vs. Amplitude (Gain = 0 dB, fIN = 1 kHz, 80 kHz Low-Pass Figure 9. THD + N vs. Supply Voltage (AV = 0 dB, VIN = 1 V rms, fIN = 1 kHz, 80
Filter) kHz Low-Pass Filter)

Rev. C | Page 6 of 16
Data Sheet SSM2018
500 15
TA = +25°C
TA = +25°C
VS = ±15V VS = ±15V
RF = 18kΩ

MAXIMUM OUTPUT SWING (±VPEAK )

400 12
NOISE DENSITY (nV/ Hz)

300 9

200 6

100 3

TE
0 0

00345-010

00345-013
10 100 1k 10k 100k 100 1k 10k 100k
FREQUENCY (Hz) LOAD RESISTANCE (Ω)
Figure 10. Noise Density vs. Frequency (Unity Gain, Referred to Input) Figure 13. Maximum Output Swing vs. Load Resistance (THD = 1 % Max)

25 100
TA = +25°C
TA = +25°C
RF = Ω 90 VS = ±15V
OUTPUT VOLTAGE SWING (±VPEAK )

20

15

RL =
LE OUTPUT OFFSET (mV)
80

70

60

50

10 40
SO
RL = 10kΩ 30

5 20

10

0 0
00345-011

00345-014
5 10 15 20 –80 –60 –40 –20 0 20 40
SUPPLY VOLTAGE (±V) GAIN (dB)
Figure 11. Maximum Output Swing vs. Supply Voltage Figure 14. Typical Output Offset vs. Gain
(THD = 1% Max)
B

18 10 90
TA = +25°C TA = +25°C
VS = ±15V VS = ±15V
RF = ∞Ω
MAXIMUM OUTPUT SWING (±VPEAK )

15 5 45
O

RL =

12 PHASE (Degrees)
RL = 10kΩ 0 0
GAIN (dB)

GAIN
9
–5 –45

6 PHASE
–10 –90

–15 –135
00345-015

0 100 1k 10k 100k 1M

00345-012

1k 10k 100k FREQUENCY (Hz)

FREQUENCY (Hz)
Figure 12. Maximum Output Swing vs. Frequency Figure 15. Gain and Phase vs. Frequency
(THD = 1 % Max)

Rev. C | Page 7 of 16
SSM2018 Data Sheet
60 100
TA = +25°C TA = +25°C
VS = ±15V 90 0V < VC < 1.2V
40 FREQ = 0Hz
80 300 UNITS
20
70

60
GAIN (dB)

UNITS
50
–20
40
–40 30

20
–60

10

TE
–80

00345-016
100 1k 10k 100k 1M 10M 0

00345-019
FREQUENCY (Hz) –3 –2 –1 0 1 2
CONTROL FEEDTHROUGH (mV)
Figure 16. Gain vs. Frequency Figure 19. Control Feedthrough Distribution

0.06 0
TA = +25°C TA = +25°C
VS = ±15V VS = ±15V
0.05

0.04
LE CONTROL FEEDTHROUGH (dB)

–20
VC = 100mV rms
DISTORTION (%)

VIN = +10dBu –40

AV = –20dB
0.03 AND
VIN = –10dBu
AV = +20dB –60
SO
0.02

–80
0.01 VIN = 10dBu
AV = 0dB

0 –100

00345-020
00345-017

–40 –20 0 20 40 60 80 100 100 1k 10k 100k

TEMPERATURE (°C) FREQUENCY (Hz)

Figure 17. Distortion vs. Temperature Figure 20. Control Feedthrough vs. Frequency
B

–60 3
TA = +25°C VS = ±15V
VS = ±15V 0V < VC < 1.2V
2 FREQ = 0Hz
CONTROL FEEDTHROUGH (mV)

–70
O
OUTPUT NOISE (dBu)

1
–80

–90
–1

–100
–2

–110 –3
00345-018

00345-021

–60 –40 –20 0 20 40 –40 –20 0 20 40 60 80 100

GAIN (dB) TEMPERATURE (°C)

Figure 18. Output Noise vs. Gain (VIN = GND, 20 kHz Bandwidth) Figure 21. Control Feedthrough vs. Temperature

Rev. C | Page 8 of 16
Data Sheet SSM2018
–20 0
VS = ±15V TA = +25°C
VS = ±15V

–20
–25
GAIN CONSTANT (mV/dB)

–40

CMRR (dB)
–30

–60

–35
–80

TE
–40 –100

00345-025
00345-022
–40 –20 0 20 40 60 80 100 10 100 1k 10k 100k
TEMPERATURE (°C) FREQUENCY (Hz)

Figure 22. Gain Constant vs. Temperature Figure 25. CMRR vs. Frequency

–28 15.0
TA = +25°C
TA = +25°C
VS = ±15V
12.5
–29
LE
GAIN CONSTANT (mV/dB)

SLEW RATE (V/µs)

10.0
–30
+SLEW RATE
7.5

–31
5.0
SO
–SLEW RATE
–32
2.5

–33 0

00345-026
00345-023

–80 –60 –40 –20 0 20 40 60 0 5 10 15

GAIN (dB) SUPPLY VOLTAGE (±V)

Figure 23. Gain Constant Linearity vs. Gain Figure 26. Slew Rate vs. Supply Voltage
B

0.1 0
TA = +25°C
VS = ±15V TA = +25°C
AV = 0dB VS = ±15V
VIN = 100V rms –20
0
O

+PSRR

–0.1 –40
PSRR (dB)
GAIN (dB)

–0.2 –60
–PSRR

–0.3 –80

–0.4 –100
00345-024

00345-027

100 1k 10k 100k 10 100 1k 10k 100k

FREQUENCY (Hz) FREQUENCY (Hz)
Figure 24. Gain Flatness vs. Frequency Figure 27. PSRR vs. Frequency

Rev. C | Page 9 of 16
SSM2018 Data Sheet

THEORY OF OPERATION
The SSM2018 has the same internal circuitry as the original The collector currents of Q2 and Q3 produce the output voltage.
SSM2018. The detailed diagram in Figure 28 shows the main The output of Q3 is mirrored by amplifier A1 to add to the
components of the VCA. The essence of the SSM2018 is the overall output voltage. On the other hand, the collector currents
gain core, which comprises two differential pairs (Q1–Q4). of Q1 and Q4 are used for feedback to the differential inputs.
When the control voltage, VC, is adjusted, current through the Because Pins 6 and 4 are shorted together, any input voltage
gain core is steered to one side or the other of the two differential produces an input current which flows into Pin 4. The same is
pairs. The tail current for these differential pairs is set by the true for the inverting input, which is connected to Pin 1. The
mode bias of the VCA (Class A or AB), which is labeled as IM in overall feedback ensures that the current flowing through the
the diagram. IM is then modulated by a current proportional to input resistors is balanced by the collector currents in Q1 and Q4.
the input voltage, labeled IS. For a positive input voltage, more
COMPENSATING THE SSM2018
current is steered (by the splitter) to the left differential pair; the
opposite is true for a negative input. The SSM2018 has a network that uses an adaptive compensation

TE
scheme that adjusts the optimum compensation level for a given
To understand how the gain control works, a simple example is gain. The control voltage not only adjusts the gain core steering,
best. Take the case of a positive control voltage on Pin 11. Note it also adjusts the compensation. The SSM2018 has three
that the bases of Q2 and Q3 are connected to ground via a 200 compensation pins: COMP1, COMP2, and COMP3. COMP3 is
Ω resistor. A positive control voltage produces a positive voltage normally left open. Grounding this pin actually defeats the adaptive
on the bases of Q1 and Q4. Concentrating on the left-most compensation circuitry, giving the VCA a fixed compensation
differential pair, this raises the base voltage of Q1 above that of point. The only time this is desirable is when the VCA has fixed
Q2. Thus, more of the tail current is steered through Q1 than
through Q2. The current from the collector of Q2 flows through
the external 18 kΩ feedback resistor around amplifier A3.
When this current is reduced, the output voltage is also reduced.
Thus, a positive control voltage results in an attenuation of the
LE feedback, such as the voltage controlled panner (VCP) circuit
shown later in the data sheet. Thus, for the Basic VCA circuit or
the OVCE circuit, COMP3 should be left open.

input signal, which explains why the gain constant is negative.

COMP 2 COMP 1 V –IG +I1–G
SO
V+ G
2 8 5 14 3 1

15 BAL

A1 4 –I1–G
COMPENSATION A3 A2
NETWORK A4 16 V1–G

–IN 7
1–G G G 1–G
GAIN CORE
B

1.8kΩ
Q1 Q2 Q3 Q4 11 VC

200Ω
+IN 6 13 GND
Is 200Ω Is
Im + ( ) Im – ( )
2 2
O

VREF
SPLITTER

SSM2018
12 MODE

Im
V– 10
00345-029

COMP 3

Figure 28. Detailed Functional Diagram

Rev. C | Page 10 of 16
Data Sheet SSM2018
A compensation capacitor must be added between COMP1 and IC = IS × e(VBE /VT) (2)
COMP2. Because the VCA operates over such a wide gain The factor a is a function not only of VT but also the scaling due
range, the compensation should ideally be optimized for each to the resistor divider of the 200 Ω and 1.8 kΩ resistors shown
gain. When the VCA is in high attenuation, there is very high in Figure 2. The resulting expression for a is as follows: a =
loop gain, and the part needs to have high compensation. On 1/(10 × VT), which is approximately equal to 4 at room
the other hand, at high gain, the same compensation capacitor temperature. Substituting a = 4 in the above equation results in
would overcompensate the part and roll off the high frequency a −28.8 mV/dB control law at room temperature.
performance. Thus, the SSM2018 employs a patented adaptive
compensation circuit. The compensation capacitor is Miller The −28.8 mV/dB number is slightly different from the data
connected between the base and collector of an internal sheet specification of −30 mV/dB. The difference arises from
transistor. By changing the gain of this transistor via the control the temperature dependency of the control law. The term VT is
voltage, the compensation is changed. known as the thermal voltage, and it has a direct dependency
on temperature:
Increasing the compensation capacitor causes the frequency
VT = kT/q

TE
response and slew rate to decrease, which tends to cause high
frequency distortion to increase. For the basic VCA circuit, 47 pF where
was chosen as the optimal value. The OVCE circuit described k = Boltzmann’s constant = 1.38 E − 23
later uses a 220 pF capacitor. The reason for the increase is to q = electron charge = 1.6 E − 19
compensate for the extra phase shift from the additional output T = absolute temperature in Kelvin)
amplifier used in the OVCE configuration. The compensation This temperature dependency leads to the −3500 ppm/°C drift
capacitor can be adjusted over a practical range from 47 pF to of the control law. It also means that the control law changes as

pF the frequency response is significantly degraded.

CONTROL SECTION
LE
220 pF if desired. Below 47 pF, the parts may oscillate; above 220

As noted above, the control voltage on Pin 11 steers the current

the part warms up. Thus, our specification for the control law
states that the part has been powered up for 60 seconds.
When the part is initially turned on, the temperature of the die
is still at the ambient temperature (25°C for example), but the
through the gain core transistors to set the gain. The unity gain power dissipation causes the die to warm up. With ±15 V
(0 dB) condition occurs at VC = 0. Attenuation occurs in the supplies and a supply current of 11 mA, 330 mW is dissipated.
SO
VCA for positive voltages (0 V to 3 V, typ), and gain occurs for This number is multiplied by θJA to determine the rise in the
negative voltage (0 V to −1.3 V, typ). From –1.3 V to +3.0 V, die’s temperature. In this case, the die increases from 25°C to
140 dB of gain range is obtainable. The output gain formula is approximately 50°C. A 25°C temperature change causes a 8.25%
as follows: increase in the gain constant, resulting in a gain constant of
VOUT = VIN × e(−aVC) (1) 30 mV/dB. The graph in Figure 22 shows how the gain constant
varies over the full temperature range.
The exponential term arises from the standard Ebers-Moll
equation describing the relationship of a transistor’s collector
B

current as a function of the base-emitter voltage:

O

Rev. C | Page 11 of 16
SSM2018 Data Sheet

APPLICATIONS INFORMATION
The SSM2018 is a trimless voltage controlled amplifier (VCA) for The output of the basic VCA is taken from Pin 14, which is the
volume control in audio systems. The SSM2018 is identical to output of an internal amplifier. Note that the second voltage
the original SSM2018 in functionality and pinout; however, it is output (Pin 16) is connected to the negative supply. This is
the first professional quality audio VCA in the marketplace that normal and actually disables that output amplifier, ensuring
does not require an external trimming potentiometer to minimize that it does not oscillate and cause interference problems.
distortion. Instead, the SSM2018 is laser trimmed before it is Shorting the output to the negative supply does not cause the
packaged to ensure the specified THD and control feedthrough supply current to increase. This amplifier is only used in the
performance. This has a significant savings in not only the cost of OVCE application explained in the Operational Voltage
external trimming potentiometers, but also the manufacturing cost Controlled Element section.
of performing the trimming optimization during production. The control port follows a −30 mV/dB control law. The application
BASIC VCA CONFIGURATION circuit shows a 3 kΩ and 1 kΩ resistor divider from a control
voltage. The choice of these resistors is arbitrary and could be

TE
The primary application circuit for the SSM2018 is the basic
VCA configuration, which is shown in Figure 29. This configura- any values to properly scale the control voltage. In fact, these
tion uses differential current feedback to realize the VCA. A resistors can be omitted if the control voltage has been properly
complete description of the internal circuitry of the VCA, and this scaled. The 1 μF capacitor is in place to provide some filtering
configuration, is given in the Theory of Operation section. The of the control signal. Although the control feedthrough is
SSM2018 is trimmed at the factory for operation in the basic trimmed at the factory, the feedthrough increases with frequency
VCA configuration with class AB biasing. Thus, for optimal (Figure 20). Thus, high frequency noise can feed through and
distortion and control feedthrough performance, use the same
configuration and biasing. All of the graphs for the SSM2018 in
the data sheet have been measured using the circuit of Figure 29.
50pF
LE add to the noise of the VCA. Filtering the control signal helps
minimize this noise source.
PROPER OPERATING MODE FOR THE SSM2018
The SSM2018 has the flexibility of operating in either Class A
18kΩ or Class AB. This is accomplished by adjusting the amount of
VOUT
current flowing in the gain core (IM in Figure 28). The traditional
1 16 V–
trade-off between the two classes is that Class A tends to have
SO
V+ 2 15
lower THD but higher noise than Class AB. However, by using
3 14
RB
well matched gain core transistors, distortion compensation
4 13
SSM2018T 150kΩ circuitry and laser trimming, the SSM2018 has excellent THD
1µF 5 12 V+
VIN+
18kΩ
6 11
3kΩ
VCONTROL
performance in Class AB. Thus, it offers the best of both worlds
VIN– 7 10 1µF 1kΩ
in having the low noise of Class AB with low THD.
1µF 18kΩ
00345-028

8 9 Because the SSM2018 operates optimally in Class AB, the

47pF
distortion trim is performed for this class. To guarantee
B

Figure 29. Basic VCA Application Circuit

conformance to the data sheet THD specifications, the SSM2018
In the simple VCA configuration, the SSM2018 inputs are at a must be operated in class AB. This does not mean that it can
virtual ground. Thus, 18 kΩ resistors are required to convert the not be operated in Class A, but the optimal THD trim point is
input voltages to input currents. The schematic also shows ac different for the two classes. Using Class A operation results to
O

coupling capacitors. These are inserted to minimize dc offsets 0.05% without trim. An external potentiometer could be added
generated by bias current through the resistors. Without the to change the trim back to its optimal point as shown in the
capacitors, the dc offset due to the input bias current is typically OVCE application circuit, but this adds the expense and time in
5 mV. The input stage has the flexibility to run either inverting, adjusting a potentiometer.
noninverting, or balanced. The most common configuration is The class of operation is set by selecting the proper value for RB
to run it in the noninverting single-ended mode. If either input shown in Figure 29. RB determines the current flowing into the
is unused, the associated 18 kΩ resistor and coupling capacitor MODE input (Pin 12). For class AB operation with ±15 V supplies,
should be removed to prevent any additional noise. RB should be 150 kΩ. This results in a current of 95 μA. For
The common-mode rejection in balanced mode is typically other supply voltages, adjust the value of RB such that current
55 dB up to 1 kHz, decreasing at higher frequencies as shown in remains at 95 μA. This current follows the formula:
Figure 25. To ensure good CMRR in the balanced configuration, ( V CC  0.7 V)
I MODE  (3)
the input resistors must be balanced. For example, a 1% mismatch
results in a CMRR of 40 dB. To achieve 55 dB, these resistors RB
should have an absolute tolerance match of 0.1%. The factor of 0.7 V arises from the fact that the dc bias on Pin
12 is a diode drop above ground.
Rev. C | Page 12 of 16
Data Sheet SSM2018
OUTPUT DRIVE TEMPERATURE COMPENSATION OF THE GAIN
The SSM2018 is buffered by an internal op amp to provide a CONSTANT
low impedance output. This output is capable of driving to The gain constant has a −3500 ppm/°C temperature drift due to
within 1.2 V of either rail at 1% distortion for a 100 kΩ load. the inherent nature of the control port. Over the full temperature
Note that this 100 kΩ load is in parallel with the feedback range of −40°C to +85°C, the drift causes the gain to change by
resistor of 18 kΩ, so the effective load is 15.3 kΩ. For better 7 dB if the part is in a gain of ±20 dB. If the application requires
than 0.01% distortion, the output should remain about 3.5 V the gain constant to be the same over a wide temperature range,
away from either rail as shown in Figure 6. As the graph of external temperature compensation should be employed. The
output swing versus load resistance shows (Figure 13), to simplest form of compensation is a temperature compensating
maintain less than 1% distortion the output current should be resistor (TCR) such as the PT146 from Precision Resistor Co.
limited to approximately ±1.3 mA. If higher current drive is These elements are different than a standard thermistor in that
required, the output should be buffered with a high quality op they are linear over temperature to better match the linear drift
amp such as the ADA4897-1 or the AD797. of the gain constant.

TE
The internal amplifiers are compensated for unity gain stability
CONTROL 2kΩ 1kΩ*
and are capable of driving a capacitive load up to 4700 pF. VOLTAGE
Larger capacitive loads should be isolated from the output of +15V
the SSM2018 by the use of a 50 Ω series resistor. PIN 11
OP27 SSM2108/
V+ REMOVE FOR SSM2018T SSM2108T
OFFSET
–15V
TRIM 10MΩ *PT146 AVAILABLE FROM
SYMMETRY
LE PRECISION RESISTOR CO.

00345-031
100kΩ
TRIM 10601 75TH STREET NORTH
470kΩ
LARGO, FL. 34647 (727) 541-5771
V– 500kΩ Figure 31. Two TCRs Compensate for Temperature Drift of Gain Constant
50pF
The gain constant has a −3500 ppm/°C temperature drift that is
18kΩ due to the reciprocal dependence of the design on absolute
VOUT
temperature. This causes the gain to vary by 7 dB over the
1 16
SO
temperature range from −40°C to +85°C when the nominal gain
V+ 2 15

3 14
at room temperature is set to 20 dB. The gain change is quite
4 13
small if the temperature range of operation is restricted.
SSM2018 RB
Nevertheless, the TC of the gain constant is easily compensated
1µF 5 12 V+
18kΩ 3kΩ
VIN+ 6 11 VCONTROL by buffering the control voltage to the VCA with a circuit having a
VIN– 7 10 1µF 1kΩ 3500 ppm/°C temperature coefficient. Figure 31 shows a simple
1µF 18kΩ solution to the problem using an op amp with a PT146 temperature
8 9 NC
47pF compensating resistor from the Precision Resistor Company.
NOTES V–
00345-030
B

1. RB: 150kΩ FOR CLASS AB. Note that this circuit is inverting, which changes the gain
2. NC = NO CONNECT.
constant to a positive quantity. Any other circuit that provides
Figure 30. Upgrading SSM2018 Sockets
the necessary positive TC works.
UPGRADING SSM2018 SOCKETS
O

The SSM2018 easily replaces the SSM2018 in the basic VCA

configuration. The parts are pin for pin compatible allowing
direct replacement. At the same time, the trimming potentiometers
for symmetry and offset should be removed, as shown in Figure 30.
Upgrading immediately to the SSM2018 saves the expense of
the potentiometers and the time in production of trimming for
minimum distortion and control feedthrough.
If the SSM2018 is used in the OVCE or VCP configuration, the
SSM2018 can still directly replace it; however, the potentiometers
cannot necessarily be removed, as explained in the Operational
Voltage Controlled Element and Voltage Controlled Panner
sections.

Rev. C | Page 13 of 16
SSM2018 Data Sheet
DIGITAL CONTROL OF THE GAIN The SSM2018 can be operated in single-supply mode as long as
A common method of controlling the gain of a VCA is to use a the circuit is properly biased. Figure 33 shows the proper
digital-to-analog converter to set the control voltage. Figure 32 configuration, which includes an amplifier to create a false
shows a 12-bit DAC, the DAC8512, controlling the SSM2018. ground node midway between the supplies. A high quality, wide
The DAC8512 is a complete 12-bit converter in an 8-pin package. bandwidth audio amplifier, such as the ADA4897-1 or the
It includes an on-board reference and an output amplifier to AD797, should be used to ensure a very low impedance ground
produce an output voltage from 0 V to 4.095 V, which is 1 mV/bit. over the full audio frequency range. The minimum operating
Since the voltage is always positive, this circuit only provides supply for the SSM2018 is ±5 V, which gives a minimum single-
attenuation. The resistor divider on the output of the DAC8512 supply of +10 V and ground. The performance of the circuit
is set to scale the output voltage so that full scale produces 80 dB with +10 V is identical to graphs that show operation of the
of attenuation. The resistor divider can be adjusted to provide SSM2018 with ±5 V supplies.
50pF
other attenuation ranges. If a parallel interface is needed, then
the DAC8562 may be used or, for a dual DAC, the AD8582. 18kΩ
VOUT

TE
50pF
1 16

18kΩ V+ 2 15
VOUT
3 14

NC 1 16 4 13
SSM2018T RB
+15V 2 15 NC 1µF 5 12 V+
18kΩ 3kΩ
0.1µF 3 14 VIN+ 6 11 VCONTROL
VIN– 7 10 1µF 1kΩ
4 13
150kΩ 1µF 18kΩ

VIN
18kΩ

NC 7

47pF
5

8
SSM2018T
12

11

10

9 NC 0.1µF
LE
+15V

–15V

100kΩ
47pF

V+
8

V+

OP176
9

0.1µF
+5V 100kΩ 10µF

00345-033
SO
1

CS 2
R6 Figure 33. Single-Supply Operation of SSM2018
0V ≤ VC ≤ +2.24V
CLR 6 825Ω
OPERATIONAL VOLTAGE CONTROLLED ELEMENT
8
LD 5 DAC8512 R7 CCON
1kΩ 1µF
SCLK 3
The SSM2018 has considerable flexibility beyond the basic VCA
SDI 4
circuit utilized throughout this data sheet. The name
00345-032

7
operational voltage controlled element (OVCE) comes from the
NC = NO CONNECT
fact that the part behaves much like an operational amplifier
Figure 32. 12-Bit DAC Controls the VCA Gain with a second voltage controlled output. The symbol for the
B

SUPPLY CONSIDERATIONS AND SINGLE-SUPPLY OVCE connected as a unity gain follower/VCA is shown in
OPERATION Figure 34. The voltage output labeled V1–G is fed back to the
inverting input as it is for an op amp’s feedback. The VG output
The SSM2018 has a wide operating supply range. Many of is amplified or attenuated depending upon the control voltage.
O

the graphs in this data sheet show the performance of the part
from ±5 V to ±18 V. These graphs offer typical performance Because the OVCE works similarly to an op amp, the feedback
specifications and are a good indication of the parts’ capabilities. could as easily have included resistors to add gain, or a filter
The minimum operating supply voltage is ±4.5 V. Below this network to add frequency shaping. The full application circuit
voltage, the parts are inoperable. Thus, to account for supply for the OVCE is shown in Figure 35. Note that the amplifier
variations, the recommended minimum supply is ±5 V. whose output (Pin 16) was originally connected to VMINUS is
now the output for feedback. As mentioned before, because the
For simplicity, the circuits in the data sheet do not show supply SSM2018 is trimmed for the basic VCA configuration,
decoupling; however, to ensure best performance, each supply pin potentiometers are needed for the OVCE configuration to
should be decoupled with a 0.1 µF ceramic (or other low resistance ensure the best THD and control feedthrough performance.
and inductance type) capacitor as close to the package as possible.
This minimizes the chance of supply noise feeding through the
part causing excessive noise in the audio frequency range.

Rev. C | Page 14 of 16
Data Sheet SSM2018
If a symmetry trim is to be performed, it should precede the VOLTAGE CONTROLLED PANNER
control feedthrough trim and be done as follows: An interesting circuit that is built with the OVCE building
1. Apply a 1 kHz sine wave of 10 dBu to the input with the block is a voltage controlled panner. Figure 36 shows the
control voltage set for unity gain. feedback connection for the circuit. Note that the average of
2. Adjust the symmetry trim potentiometer to minimize both outputs is fed back to the input. Thus, the average must be
distortion of the output signal. equal to the input voltage. When the control voltage is set for
gain at VG, this causes V1–G to attenuate (to keep the average the
Next, the control feedthrough trim is done as follows:
same). On the other hand, when VG is attenuated, V1–G is
1. Ground the input signal port and apply a 60 Hz sine wave amplified. The result is that the control voltage causes the input
to the control port. The sine wave should have its high and to pan from one output to the other. The following expressions
low peaks correspond to the highest gain to be used in the show how this circuit works mathematically:
application and 30 dB of attenuation, respectively. For
VG = 2 K × VIN and VI−G = 2(1 − K) × VIN (4)
example, a range of 20 dB gain to 30 dB attenuation
requires that the sine wave amplitude ranges between where K varies between 0 and 1 as the control voltage is

TE
−560 mV and +840 mV on Pin 11. changed from full attenuation to full gain, respectively.
2. Adjust the control feedthrough potentiometer to null the When VC = 0, then K = 0.5 and VG = V1–G = VIN. Again,
signal seen at the output. trimming is required for best performance. Pin 9 must be
VC grounded. This is possible because the feedback is constant and
VG the adaptive network is not needed. The VCP is the only
VIN application shown in this data sheet where Pin 9 is grounded.
LE VC
00345-034

V1–G
VG
VIN
Figure 34. OVCE Follower/VCA Connection
V1–G
18kΩ
V+

00345-036
CONTROL 50pF
18kΩ
SO
FEEDTHROUGH
TRIM 18kΩ
100kΩ V1–G Figure 36. Basic VCP Connection
10MΩ SYMMETRY
TRIM 470kΩ
500kΩ
V– 50pF

18kΩ
VG

1 16
B

V+ 2 15

3 14

4 13
SSM2018 RB
5 12 V+
+ 3kΩ
6 11 VCONTROL
O

INPUTS –
7 10 V– 1µF 1kΩ

8 9 NC
220pF
NOTES
1. RB = 30kΩ FOR CLASS A.
00345-035

150kΩ FOR CLASS B.

2. NC = NO CONNECT.

Figure 35. OVCE Application Circuit

Rev. C | Page 15 of 16
SSM2018 Data Sheet

OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)

16 9 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
8
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC
0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)

TE
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001-AB

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

073106-B
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

ORDERING GUIDE
LE
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 37. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)

Model 1 Temperature Range Package Description Package Option

SSM2018PZ –40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
SO
SSM2018TPZ –40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
1
Z = RoHS Compliant Part.
B
O

©2002–2013 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D00345-0-2/13(C)

Rev. C | Page 16 of 16