ON THE CIRCUIT ORIENTED AVERAGE LARGE-SIGNAL

MODELING OF SWITCHING POWER CONVERTERS AND

ITS APPLICATIONS

Carlos Eduardo Cuadros Ortiz

Dissertation submitted to the Faculty of the Virginia Polytechnic Institute and State
University in partial fulfillment of the requirements for the degree of

Doctor of Philosophy
in
Electrical Engineering

Dushan Boroyevich, Chairman

Douglas Lindner
Jacobus Van Wyk
Ricardo Burdisso
Virgilio Centeno
William Baumann

August 8, 2003

Blacksburg, Virginia

Keywords: average modeling, slow dynamics manifold, PWM converters, ZVS and
ZVZCS full-bridge converters, soft-switched three-phase buck rectifier, space vector
modulation.
ON THE CIRCUIT ORIENTED AVERAGE LARGE-SIGNAL
MODELING OF SWITCHING POWER CONVERTERS AND
ITS APPLICATIONS

Carlos Eduardo Cuadros Ortiz

ABSTRACT

A systematic and versatile method to derive accurate and efficient Circuit

Oriented Large Signal Average Models (COLSAMs) that approximate the slow dynamics
manifold of the moving average values of the relevant state variables for Pulse-Width
Modulated (PWM) dc to dc and three-phase to dc power converters is developed. These
COLSAMs can cover continuous conduction mode (CCM) as well as discontinuous
conduction mode (DCM) of operation and they are over one order of magnitude cheaper,
computation wise, than the switching models. This method leads primarily to simple and
effective input-output oriented models that represent transfer as well as loading
characteristics of the converter. Sine these models consist of time invariant continuous
functions they can be linearized at an operating point in order to obtain small-signal
transfer functions that approximate the dynamics of the original PWM system around an
orbit.

The models are primarily intended for software circuit simulators (i.e. Spice
derived types, Saber, Simplorer, etc), to take advantage of intrinsic features such as
transient response, linearization, transfer function, harmonic distortion calculations,
without having to change simulation environment. Nevertheless, any mathematics
simulator for ordinary differential equations can be used with the set of equations
obtained through application of Kirchoff’s laws to the COLSAMs. Furthermore, the
COLSAMs provide physical insight to help with power stage and control design, and
they allow easy interconnection among themselves, as well as with switching models, for
complete analysis at different scales (time, signal level, complexity; interconnectivity).
 A new average model for the Zero-Voltage Switched Full-Bridge (ZVS-FB)
PWM Converter is developed with the above method and its high accuracy is verified
with simulations from a switching behavioral model for several circuit component values
for both CCM and DCM.

Intrinsic positive damping effects and special delay characteristics created by an

energy holding element in a saturable reactor-based Zero-Voltage Zero-Current Switched
Full-Bridge (ZVZCS-FB) PWM converter are explained for the first time by a new
average model. Its large signal predictions match very well those from switch model
simulations whereas its small-signal predictions are verified with experimental results
from 3.5 kW prototype modules. The latter are used in a multi-module converter to
supply the DC power bus in and aircraft. The design of control loops for the converter is
based on the new model and its linearization.

The ZVZCS-FB PWM converter’s average model above is extended to deal with
interconnection issues and constraints in a Quasi-Single Stage (QSS) Zero-Voltage Zero-
Current Switched (ZVZCS) Three-Phase Buck Rectifier. The new model reveals strong
nonlinear transfer characteristics for standard Space Vector Modulation (SVM), which
lead to high input current distortion and output voltage ripple inadmissible in
telecommunications applications. Physical insight provided by this average model led to
the development of a combined modified SVM and feed-forward duty-cycle
compensation scheme to reliably minimize the output voltage ripple. Experimental results
from a 6 kW prototype validate large signal model for standard and modified SVM, with
and without duty-cycle compensation scheme.
 ACKNOWLEDGEMENTS

I would like to express my sincere appreciation to my advisor, Prof. Dushan

Boroyevich, for his guidance, encouragement, patience and support through the course of
this work.

I also wish to thank Profs. William Baumann, Ricardo Burdisso, Virgilio

Centeno, Douglas Lindner and, Jacobus van Wyk for their contributions and suggestions
as members of my committee.

Special thanks are due to my fellow classmates Sriram Chandrasekaran and

Kunrong Wang for writing the control program, designing and building the prototype and
discussing technical issues for the three-phase rectifier. Without their help, this work
would not have been possible.

In addition, I would like to thank all the faculty, staff and students at CPES for all
their support, collaboration and friendship.

iv
 To

Ligia,

Maria Fernanda

and

Miguel Eduardo
 Table of Contents

1. INTRODUCTION.……………………………………………………………1
1.1. Motivation and Goals…………………………………………………………...1
1.2. Literature Review……………………………………………………………….2
1.3. Dissertation Outline and Major Results………………………………………6

2. MATHEMATICALDESCRIPTION OF SWITCHING POWER

CONVERTERS AND THEIR LARGE SIGNAL AND SMALL-
SIGNAL MODELING………………………………………………………..9
2.1. Characteristics and State-Space Description of PWM Converters………….9
2.1.1. Continuous-time state-space equations……………………………….…...9
2.1.2. Sampled-data state-space equations……………………………………...11
2.1.3. Sampled-data modeling of a simple PWM converter……………….…...12
2.2. Generalized Method of Averaging for PWM Converters……………..…….18
2.2.1. Procedures of the method………………………………………….….….19
2.2.2. Illustration of the generalized method of averaging for a simple
PWM Converter………………………………………………………….20
2.2.3. Generalized method of averaging for the open loop buck converter….…23
2.3. Averaging Method for Two-Time Scale PWM Converters…………………24
2.3.1. State-space description for two-time scale PWM converters……………24
2.3.2. Practical procedure for the method………………………………………25
2.4. Synthesis Method for Averaged Circuit Models of PWM Converters…......26
2.4.1. In place-averaging……………………………………………………..…26
2.4.2. PWM switch equivalent circuits…………………………………………29
2.5. Analysis of Strengths and Weaknesses of these Methods…………………...30
2.6. A New Procedure for Averaged Circuit Models…………………………..…34
2.6.1. Philosophy of the new average modeling procedure………………….…34
2.6.2. Steps of the new average modeling procedure and their guidelines…..…35
2.6.3. Application of the new procedure to the buck converter……………...…36
2.6.4. Model verification and comments…………………………………….…40

3. MODELING OF THE ZVS-FB PWM CONVERTER……………….…..58

3.1. ZVS-FB Converter Operation………………………………..……………….58
3.1.1. CCM operation…………………………………………….………….…58
3.1.2. DCM operation…………………………………………………………..53
3.2. New Averaged Circuit Model for the ZVS-FB Converter………………..…64
3.2.1. Step 1: Fast/slow classification of state variables……………………..…64
3.2.2. Step 2: LTI input/output parts……………………………………………65
3.2.3. Step 3:“Independent” variable drawn from LTI input network and
“Dependent” variable delivered to LTI output network………………...65
3.2.4. Step 4: Calculation of one-cycle average for the variables in the
previous step…………………………………………………………….65
3.2.5. Step 5: Calculation of algebraic constraints……………………………..67

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 3.2.6. Step 7: Implementation of circuit oriented simulation…………………..67
3.3. Previous Average Models for the ZVS-FB Converter……………………….68
3.4. Simulation Results……………………………………………………………..68
3.4.1. Transient simulations for parameter set 1………………………………..68
3.4.2. Transient simulations for parameter set 2………………………………..69
3.4.3. Transient simulations for parameter set 3………………………………..69
3.4.4. Transient simulations for parameter set 4………………………………..70
3.4.5. Transient simulations for parameter set 5………………………………..71
3.4.6. Transient and small-signal simulations results…………………………..71

4. MODELING OF THE SATURABLE INDUCTOR BASED

ZVZCS-FB-PWM DC-DC CONVERTER………………………………...93
4.1. ZVZCS-FB-PWM Converter Operation……………………………………..93
4.1.1. CCM operation………………………………………………………..….93
4.1.2. DCM operation…………………………………………………………..99
4.2. New Average Circuit Model for the ZVZCS-FB Converter…………….....100
4.2.1. Step 1: Fast/slow classification of state variables………………………100
4.2.2. Step 2: LTI input/output parts…………………………………………..102
4.2.3. Step 3: “Independent” variable drawn from LTI input network and
“Dependent” variable delivered to LTI output network………………...102
4.2.4. Step 4: Calculation of one-cycle average for the variables in the
Previous step……………………………………………………………102
4.2.5. Step 5: Calculation of algebraic constraints…………………………….105
4.2.6. Step 7: Implementation of circuit oriented simulation…………………105
4.2.7. Identification and modeling of energy holding elements in fast
dynamic subsystems…………………………………………………….105
4.3. Simulation Results……………………………………………………………112
4.3.1. Transient simulations for parameter set 1………………………………112
4.3.2. Transient simulations for parameter set 2………………………………117
4.3.3. Transient simulations for parameter set 3………………………………117
4.3.4. Transient simulations for parameter set 4………………………………117
4.3.5. Transient simulations for parameter set 5………………………………125
4.3.6. Transient simulations for parameter set 6………………………………125
4.4. Dynamics Comparison among Buck, ZVS-FB and ZVZCS-FB
Converters ……………………………………………………………………125
4.4.1. Transient response and small-signal transfer function from new
average model and its linearization…………………………………….125
4.4.2. Small-signal experimental results………………………………………126

5. MODELING AND MODULATION SCHEME FOR QSS-ZVZCS

THREE-PHASE BUCK RECTIFIER……………………………………136
5.1. Three-Phase Buck Rectifier………………………………………………….136
5.1.1. Three-phase buck rectifier averaged model…………………………….142
5.1.2. Three-phase buck rectifier with single-loop control……………………145
5.1.3. Modified SVM (swapping)……………………………………………..145
5.2. QSS-ZVZCS Three-Phase Buck Rectifier Operation……………………...145

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 5.2.1. Three-phase buck rectifier and ZVZCS-FB converter synchronization..145
5.2.2. QSS-ZVZCS three-phase buck rectifier operation with standard SVM..145
5.2.3. Topological stages and analytical description………………………….147
5.3. New Average Circuit Model for the QSS-ZVZCS Rectifier………...153
5.3.1. Step 1: Fast/slow classification of state variables………………………153
5.3.2. Step 2: LTI input/output parts…………………………………………..153
5.3.3. Step 3: “Independent” variable drawn from LTI input network and
“Dependent” variable delivered to LTI output network………………...153
5.3.4. Step 4: Calculation of one-cycle average for the variables in the
previous step……………………………………………………………153
5.3.5. Step 5: Calculation of algebraic constraints…………………………….157
5.3.6. Step 7: Implementation of circuit oriented simulation…………………157
5.3.7. Modeling of energy holding elements in fast dynamic subsystems……157
5.4. Analysis of Variable Distortion……………………………………….160
5.5. Hardware Implementation……………………………………………160
5.5.1. Implementation of digital controller……………………………..161
5.5.2. Implementation of decoder logic………………………………...161
5.6. Software Implementation……………………………………………...164
5.6.1. Synchronization with input voltages……………………………………164
5.7. Compensation Scheme for Standard SVM………………………………….164
5.8. Compensation Scheme for Modified SVM…………………………...170
5.9. Compatibility of Modified SVM and Compensation Scheme with
Single Input Control
Strategy…………………………………………………………………173

6. CONCLUSIONS……………………………………………………………176

7. REFERENCES……………………………………………………………..178

A Saber Template and Schematics for Buck Converter………………..….194

B Saber Templates for ZVS-FB Converter Average Models………….…..197

C Analysis and Design Procedure for Saturable Reactor-Based

Zero-Voltage Zero-Current Switched, Full-Bridge Converter
and Saber Template for its Average Model……………………………….202

D Modified Equations for Cases 2 and 3 of QSS-ZVZCS Three-Phase

Buck Rectifier Operation and for Compensated First Duty-Cycle for
Case 1 ……………………………………………………………………….224

VITA……………………………………………………………………………229

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 LIST OF FIGURES

2.1. PWM converter structure………………………………………………………...10

2.2 Simple buck PWM converter with current feedbac……………………………...14
2.3. Buck converter circuit topologies………………………………………………..15
2.4 Relevant waveforms for duty-cycle calculation…………………………………16
2.5. Partition of PWM converter structure……………………………………………31
2.6. The PWM switch………………………………………………………………...32
2.7. PWM-switch equivalent average circuit………………………………………....33
2.8. Starting point for new average modeling procedure……………………………..41
2.9. Step 1: Slow/fast variables separation……………….…………………………..42
2.10. Step 2: Identification of Linear Time Invariant input/output parts..…….……….43
2.11. Step 3: Identification of “dependent” variable drawn from input and
“independent” variable delivered to output LTI parts……………….….……….44
2.12. Step 4: Calculation of controlled source one-cycle average……………………..45
2.13. Step 5: Calculation of algebraic constraints……………………….……………..46
2.14. Step 6: Incorporation of feedback loop….……………………………………….47
2.15. Step 7: implementation of circuit simulator oriented average model……………48
2.16. Average circuit model for buck converter in CCM operation …………………..49
2.17. Buck converter in DCM operation……………………………………………….50
2.18. Average circuit model for buck converter in DCM …......………………………51
2.19. Average circuit models for buck converter in CCM and DCM operation……….52
2.20. Input/output structure average circuit models for buck converter in CCM and
DCM operation ………………………………………………………………….53
2.21. Analog computation of d2……………….…………………………………….…54
2.22. Analog computation of d and d2 with feedback loop…………………………….55
2.23. Simulation results from average (red-dashed) and switch (green-solid) mode.
Top: duty ratios, middle: inductor current, bottom: output voltage………….…..56
2.24. Simulation results from average (red-dashed) and switch (green-solid) mode….57

3.1. ZVS-FB PWM converter…………………………….…………….…………….60

3.2. Typical ZVS-FB PWM converter waveforms in CCM………………………….61
3.3. Typical ZVS-FB PWM converter waveforms in DCM…………………….……65
3.4. ZVS converter equivalent average models and waveforms in CCM…….………72
3.5. ZVS converter equivalent average model and waveforms in DCM……………..73
3.6. Analog schematic for computation of Dtrf and D2………….……………………74
3.7. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average(black) models for parameter
set 1 with zero initial state for all models………………………………………..75
3.8. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 1 with zero initial state for all models………………………..…...76
3.9. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter
set 1 with zero initial state for all models……………………..…………………77

ix
3.10. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 1 with zero initial state for all models…………………………….78
3.11. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 2 with zero initial state for all models………………...…………..79
3.12. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 2 with zero initial state for all models…………………………….80
3.13. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 2 with zero initial state for all models……………..……………..81
3.14. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 3 with zero initial state for all models…………………..………...82
3.15. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 3 with zero initial state for all models………………….…………83
3.16. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 3 with zero initial state for all models…………………………….84
3. 17. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 4 with zero initial state for all models…………………………….85
3.18. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 4 with zero initial state for all models…………………………….86
3.19. Duty ratios (top), filter inductor current (middle) and capacitor voltage
(bottom) from switching (green), new average (pink) and previous average
(black) models for parameter set 5 with zero initial state for all models………...87
3.20. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for
parameter set 5 with zero initial state for all models…………………………….88
3.21. Capacitor voltage (top) and filter inductor current (bottom) transient response
from new average models for Buck (red), ZVS-FB (blue) and ZVZCS-FB
(black) converters with parameter set I ………………………………..………..89
3.22. Capacitor voltage (top) and filter inductor current (bottom) transfer functions
from new average models for Buck (red), ZVS-FB (blue) and ZVZCS-FB
(black) converters with parameter set I …………………………………………90
3.23. Capacitor voltage (top) and filter inductor current (bottom) transient response
from new average models for Buck (red), ZVS-FB (blue) and ZVZCS-FB
(black) converters with parameter set II ………………………………...………91
3.24. Capacitor voltage (top) and filter inductor current (bottom) transfer functions
from new average models for Buck (red), ZVS-FB (blue) and ZVZCS-FB
(black) converters with parameter set II.……………………………………..….92

x
4.1. ZVZCS converter………………………………………………………………...94
4.2. ZVZCS-FB PWM primary and filter inductor current waveforms in CCM…….96
4.3. ZVZCS-FB PWM primary and filter inductor current waveforms in DCM...…..98
4.4. ZVZCS converter equivalent average models and waveforms in CCM………..101
4.5. Calculation of average blocking capacitor voltage……………………………..103
4.6. Analog computation of Dtrf and D2………………….…………………………106
4.7. Analog implementation of dynamic relationship between filter inductor
current an blocking-capacitor peak voltage ……………………………………107
4.8. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), first average (blue) and second average (pink) models for parameter
set 1 with zero initial state for all models……………………………...……….109
4.9. Zoom in of filter inductor current and capacitor voltage from switching
(green), first average (blue) and second average (pink) models for parameter
set 1 with zero initial state for all models…………………..…………………..110
4.10. Zoom in of filter inductor current and capacitor voltage from switching
(green), first average (blue) and second average (pink) models for parameter
set 1 with zero initial state for all models………………………………………111
4.11. Whole transient and zoom in of filter inductor current and capacitor voltage
from switching (green) and second average (pink) models for parameter
set 1 with zero initial state for all models………………………………………113
4.12. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero
initial state for all models ………………………………..…………………….114
4.13. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero
initial state for all models ………………………………..……………………..115
4.14. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero
initial state for all models ………………………………..……………………..116
4.15. Whole transient of filter inductor current and capacitor voltage from
switching (green) and second average (pink) models for parameter set 2
with zero initial state for all models.………………………………..…………..118
4.16. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 2 with zero
initial state for all models ………………………………..……………………..119
4.17. Whole transient of filter inductor current and capacitor voltage from
switching (green) and second average (pink) models for parameter set 3
with zero initial state for all models ………………………………..…………..120
4.18. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 3 with zero
initial state for all models ………………………………..……………………..11
4.19. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 3 with zero
initial state for all models……………………………………………………….122

xi
4.20. Whole transient and zoom in of filter inductor current and capacitor voltage
from switching (green) and second average (pink) models for parameter
set 4 with zero initial state for all models………………………………………123
4.21. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 4 with zero
initial state for all models ……………………………………….……………...124
4.22. Whole transient and zoom in of filter inductor current and capacitor voltage
from switching (green) and second average (pink) models for parameter
set 5 with zero initial state for all models………………………………………127
4.23. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 5 with zero
initial state for all models …………………………………………………...….128
4.24. Whole transient and zoom in of filter inductor current and capacitor voltage
from switching (green) and second average (pink) models for parameter
set 6 with zero initial state for all models……………………………...……….129
4.25. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 6 with zero
initial state for all models ……………………………………………...130
4.26. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVS-FB (blue) and
ZVZCS-FB (black) converters with parameter set I……………………………131
4.27. Control to capacitor voltage (top) and control to filter inductor current
(bottom) transfer functions from new average models for Buck (red),
ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set I………132
4.28. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVS-FB (blue)
and ZVZCS-FB (black) converters with parameter set II ……………………...133
4.29. Control to capacitor voltage (top) and control to filter inductor current
(bottom) transfer functions from new average models for Buck (red),
ZVS-FB (blue) and ZVZCS-FB (black) converters with parameter set II……..134
4.30. Experimental control to capacitor voltage (top) transfer for Buck and
ZVZCS-FB converters with parameter set II ………………………………….135

5.1. QSS-ZVZCS three-phase rectifier………….…………………………………..137

5.2. Three-phase buck rectifier and electric sectors…………………………………138
5.3. Three-phase buck rectifier with standard SVM ………………………....……..140
5.4. Three-phase buck rectifier ideal SVM operation ………………….…………...141
5.5. Three-phase buck rectifier average model structure………………………..…..143
5.6. Three-phase buck rectifier SVM with and without swapping…………………144
5.7. Synchronization between three-phase buck rectifier and ZVZCS-FB
converter………………………………………………………………………..146
5.8. QSS-ZVZCS rectifier typical waveforms and switch structures……………….148
5.9. QSS-ZVZCS PWM rectifier average model structure………………………….150
5.10. Calculation of average blocking capacitor voltage……………………….…….152
5.11. QSS-ZVZCS rectifier desired and experimental waveforms with typical
SVM operation…………………..……………………………………………..154

xii
 5.12. QSS-ZVZCS rectifier equivalent primary and secondary duty-cycles cases
with typical SVM operation……………………...……………………………..155
5.13. Three-phase buck rectifier (solid) and QSS-ZVZCS rectifier simulated
effective (dashed) primary and secondary duty-cycles for whole line cycle
with SVM……………………………………………………………………….158
5.14. Normalized QSS-ZVZCS rectifier simulated and experimental duty-
cycles, compensation with SVM and phase voltage …………………………...159
5.15. QSS-ZVZCS rectifier open-loop experimental phase voltage and currents
and output voltage ripple with SVM, before and after compensation for
360V peak line voltage, 48V output voltage and 40A load current…………….162
5.16. Control block diagram…………………………….……………………………163
5.17. QSS-ZVZCS rectifier power stage for 208-380V line voltage, 48V output
voltage, 6 kW output power and 40 kHz switching frequency…………………165
5.18. QSS-ZVZCS rectifier closed-loop experimental phase voltage and currents
and output voltage ripple with SVM, before and after compensation for
360V peak line voltage, 48V output voltage and 40A load current…………….166
5.19. QSS-ZVZCS rectifier simulated and experimental duty-cycles and
compensation with modified (duty-cycle order swapping) SVM………………168
5.20. QSS-ZVZCS rectifier phase currents and secondary rectifier voltage at
swapping border (phase voltage crossing) with modified SVM ……………….169
5.21. QSS-ZVZCS rectifier open-loop experimental output voltage ripple, phase
current and voltage with modified SVM, before and after compensation
for 360V line voltage, 48V output voltage and 40A load current …….……….171
5.22. QSS-ZVZCS rectifier closed-loop experimental output voltage ripple,
phase current and voltage with modified SVM, after compensation for
360V line voltage, 48V output voltage and 40A load current………………….172
5.23. QSS-ZVZCS rectifier closed-loop response to step load disturbance
(1.6 Ohm load switched in) with swapping and compensated duty cycles
for 380V peak line voltage, 48V output voltage and 1.1 Ohm initial load……..174
5.24. QSS-ZVZCS rectifier closed-loop response to step load disturbance
(1.0 Ohm load switched in) with swapping and compensated duty cycles
for 380V peak line voltage, 48V output voltage and 1.1 Ohm initial load……..175

xiii
 LIST OF TABLES

1. Parameter value sets for transient response of ZVS-FB converter.……………...68

2. Parameter value set I for small-signal model and transient response of Buck,
ZVS-FB and ZVZCS-FB converters…………………………….………………69
3. Parameter value set II for small-signal model and transient response of Buck,
ZVS-FB and ZVZCS-FB converters…………………………………………….70
4. Parameter set values for transient simulations …………………………………112

xiv
1. INTRODUCTION

1.1. Motivation and Goals

Switching power converters have become ubiquitous in consumer products as

well as in industrial, medical, and aerospace equipment due to their high efficiency, low
volume and weight, fast dynamic response, and low cost. Even though extensive efforts
and resources are continuously devoted to new component technologies and converter the
development of versatile modeling techniques suitable for general switching power
converters is still lagging.

This dissertation aims at reducing that gap by providing a systematic approach to

the development of accurate and computationally efficient but still intuitively simple
circuit oriented, average large-signal models for pulse-width modulated (PWM) full-
bridge (FB) derived, dc to dc and three-phase to dc power converters. Since a large
number of new converter topologies based on these structures have emerged lately,
versatile and reliable models are needed to speed up exploitation of their full potential.

The objectives of the circuit oriented, continuous-time, large-signal average

models developed here are, besides allowing very fast simulation times and reduced
memory space with respect to discrete and switching models, to gain physical insight, to
guarantee complete representation of large and small-signal behavior and to overcome
limitations of existing average models by including discontinuous conduction mode
(DCM) and continuous conduction mode (CCM) operation and storage element effects in
the form of algebraic and/or dynamic constraints to handle large and asymmetric ripple
components as well as feedback loops. This approach makes the new models very useful
in large signal analysis and design of single-stage single and multi-module converters, as
well as multistage converters, together with their respective input and output filters. In
addition, the new models can be linearized at an operating point to derive a small-signal
model that closely approximates the behavior around an orbit for the original system, and
hence, provides a solid starting point for control design. As a result, thorough studies of

1
interaction effects and trade-offs amongst power stage(s) and filter(s) structures, current
and voltage ripple, harmonic distortion, modulation scheme, control loop(s), stability,
transient response, to name a few, can be conducted.

The systematic modeling procedure allows for easy adaptation of the models to
perform analyses at different scales, such as time, signal level, complexity,
interconnectivity. Model extension for hybrid simulation, i.e. mixing of average and
switching models, can be easily carried out to accelerate analysis of specific subsystems
in multi-stage and/or multi-module converters.

Even though the new circuit oriented average models can be used with any
commercial mathematics software that allows simulation of ordinary differential
equations, one of the major motivations for this work is to take advantage of common
features in commercial circuit simulators, i.e. transient response, linearization, transfer
function, harmonic distortion calculations; to help with power converters analysis and
design issues without having to change simulation environment.

1.2. Literature Review

Most of the references mentioned in this work have excellent reference lists
therein, which are also assumed referenced and that are omitted here for compactness.

Switching power converters can be mainly classified according to the type of

input (ac or dc) and output (ac or dc) variables [E5, M7]. Further classifications with
respect to parameters such as control variable, PWM, or frequency modulation, [E5, M7],
waveform, i.e. piece wise linear or resonant [E5, M7], switching stresses, i.e. hard or soft
[E5, J4, M7, H3, V6, V7], among others, are well known.

Most common PWM power converters have switch transitions determined by

control and state variables through constraint equations [B6, B11, B12, C5, C7, C8, C20,

2
E1, E3, E5, F1, G1, H6, K7, L2, M7, O3, S4, T8, V3, X2], and in between those
transitions the converters are very accurately described by linear autonomous ordinary
differential equations. Sampled-data models [A1, B6, B12, F1, G1, G3, H4, L2, L13,
L15, M5, P1, T7, V3, V4] are suitable to represent and to simulate these converters at
switching instants, but they lack information between samples and are computationally
expensive. However, the closed-loop operation can be accurately described and
characterization (Poincare maps) of iterative maps for instability, bifurcation and chaotic
behavior analysis can be easily obtained [A2, B2, C3, C17, D1, F4, H1, J1, L3, P4, S24,
T3]. Large signal stability of PWM and quasi-resonant converters through nonlinear
modeling and control has also been discussed in [C4, C17, E3, F2, G3, H6, L17, S18,
S19]. From all of these large signal approaches, continuous-time small-signal models can
be obtained through linearization around a periodic trajectory (orbit). When the starting
model is discrete subsequent transformation of the results into continuous time is needed
[F1, F3, L2, S17, T7, V3, W5].

Small-signal models have also been obtained from very dissimilar perspectives
such as model fitting with neural networks of data from converter simulations [H5, L7],
analytical approximations [E2, V11, W4], and perturbation of exponential transition
matrices either on computer [M4, W5] or on state plane graphs [O4].

The well-known state-space averaging method [B11] can also be developed as

the low-order approximation in several different methods by retaining only the first terms
in:
(a) power series for the matrix exponentials in the sample-data modeling [V3],
(b) multi-frequency averaging [C1],
(c) the generalized method of averaging [K6, L4, L6, N3, S2, S13, V3, W3].

It provides information about the average of the state variables, but loses
accuracy in the high frequency range, i.e. near a half of the switching frequency, and/or
when the filter time constants are close to the switching period, as it usually happens in
some of the sampled-data models above. Similar characteristics with slight result

3
improvements are exhibited by the current injection-absorption method [K5], by the
averaged PWM-switch model [V8] and its several extensions for multi-switch PWM
converters and resonant converters, and by several other circuit-oriented average models
[A3, C5, C6, C7, C24, E4, J5, L9, L11, K4, M2, M6, N2, R1, O1, O2, R1, S4, S6, S7, S8,
S20, T4, T8, V1, V8, V9, V10, W3, W7, X2, X4, Y2].

Validity of the method of averaging to simple PWM converter topologies was

rigorously proved [B3, K6, L4, S2] and extended to provide frequency-dependent
continuous-time average models for open and closed-loop operation [B5, L5, L6].
Unfortunately, application of this technique or the familiar state-plane portrait methods
[G2, O3, S10], useful to analyze operation of low order resonant converters, to more
complex soft-switched power converters becomes almost intractable. Analytic
approximations and modifications to the method of averaging have also been proposed
for PWM and some types of resonant converters [N3, S13, S14, S22, W3, X3].

Extended describing functions and multi-frequency methods [C1, C18, S3, Y1]
overcome this tractability problem and had been proven useful in small-signal analysis of
resonant and multi-resonant converters of any order, despite their lack of physical insight
and the need for special software.

Some special simulator programs and/or algorithms have been developed to

provide shorter simulation times [B6, B7, L8, M1, N1, P2, S5, T2, D2, B9, B10] at the
expense of limited functionality and data preparation.

Following the attempt made in [R4], a corrected and general continuous-time,

state-space, small-signal model of current programmed PWM converters was developed
in [T5, T7] and verified with the so called exact small-signal models obtained by
application of time varying transfer functions [T6, T9]. However none of these papers
discusses relevance of time varying effects at frequencies near a half of the switching
frequency which are detailed in [P3] and analyzed for three-phase PWM modulators in

4
[H2]. The same happens in [K5, S16, S21, S24, T1, V8, V10] where attempts to fit and/or
explain small-signal measurements in the high frequency range were made without
dealing with the stochastic characteristics of those measurements. Furthermore, extensive
similar work on small-signal modeling of the modulator and/or the whole converter for
peak and average current control has been reported in [B8, C19, K1, K8, L10, P5, R5,
S23, S24, T1, X1].

Geometrical linearization through graphical analysis of perturbed steady-state

waveforms was used in [V5] to provide an approximate small-signal model of the widely
used Zero-Voltage Switched, Full-Bridge (ZVS-FB) PWM converter [S1] based on the
PWM switch model. An approximate large signal model whose usage is restricted to a
narrow range in CCM and a small-signal model derivation along the lines of [S1] for the
ZVS-FB converter was presented in [T4]. Similarly small-signal models for some ZVS
and Zero-Voltage Zero-Current Switched Full-Bridge ZVZCS-FB converters are
developed in [C15, X5].

Lately, with the progress in symbolic math packages, methods to obtain closed
form expressions for large and small-signal models of PWM converters have been
developed [B4, S12]. These methods separate fast and slow dynamic subsystems in the
converter and describe their interaction through an algebraic equation. However, they do
not allow for non-linear or energy holding components in the fast dynamic subsystem or
high order systems for which closed form solutions cannot be computed. Therefore they
cannot be applied to many new soft-switched topologies [B1, C9, C10, C11, C12, C16,
J2, J3, J4, K2, K3, L1, L12, L14, M3, V6, V7, W1, W2, W6, X5].

From a different perspective, power transfer based models [S7, S8, E5] provide
good low frequency description of input-output characteristics for certain PWM
converters when loss-less switching devices are considered. When losses are included,
the principle of energy conservation needs to be invoked [C24]. These approaches, when
combined with other models such as current injection-absorption, state-space averaging,

5
PWM and resonant switch, are useful in model verification as well as in calculation of
input and output impedances for subsystem interaction analysis [C13, G2, R3].

A few attempts to develop a SPICE oriented dual model to deal both with CCM &
DCM were plagued with convergence problems [C7, G4, S21]. In [R5] the same authors
of [C7] presented a revised version that solved those problems for the buck converter. A
decade later the subject was retaken in [N4] where dual models for most of the simple
PWM converters are presented.

As a matter of completeness the following special modeling approaches are also

mentioned: geometric [S9], phasor transformation [R2], switching flow graph [S11],
virtual winding for transformer magnetizing current [L16].

For the modeling presented here on the three-phase buck rectifier and a ZVZCS
three-phase to dc converter the wonderful theses [H2, N2] and the references therein
provide all the needed background.

1.3. Dissertation Outline and Major Results.

1. Mathematical description of large signal average models for switching power

converters. The next chapter reviews analytical procedures for variations of the
generalized method of averaging [K6, S13] proposed for switching power
converters (SPCs). The theoretical foundation behind a method to synthesize
averaged circuits models for SPCs [S4] is also presented. Scope and limitations of
these methods are discussed. A new systematic procedure to derive circuit
oriented average models, which describe input-output characteristics for PWM
converters, and that overcomes several of those limitations is developed. This
procedure combines the theoretical foundation of [S4] with variations of some
ideas from in-place circuit averaging techniques in [V8, V9], extensions to
constraints derivation to keep them valid during transient conditions [V3],

6
 practices from analog and circuit simulation in order to model CCM-DCM
bifurcation [R5] and heuristic guidelines for selecting averaged circuit structure
and relevant states as well as for modeling energy storage components. Basic
features of the new modeling procedure are introduced by applying it to a simple
buck PWM converter. CCM and DCM operation is covered by the same average
model.

2. Modeling of the ZVS-FB PWM converter. In Chapter 3 a new and very

accurate average model for both DCM and CCM mode of operation is developed
and its superiority compared to existing models is clearly seen for different
parameter and load values. Small-signal models obtained through linearization of
the new average model at different operating points show strong positive damping
effects, i.e. intrinsic negative feedback, over the output filter. These results agree
very well with those from experiments.

3. Modeling of a saturable reactor-based ZVZCS-FB PWM converter.

Extension of the circuit averaging procedure to include new effects created by a
saturable reactor and a so-called energy holding component, in power converter
modeling literature, provided the only reported model for this ZVZCS converter.
The model, detailed in Chapter 4, explains and recreates the interaction of power
stage components, which leads to negative damping effects, i.e. intrinsic positive
feedback, over the output filter. These effects were also reported for the first time
with the model. Large signal simulation results from the average circuit model
closely match those from a switching model for different parameter and load
values. Small-signal models from linearization of the average circuit model,
which correctly predicted the negative damping effects seen in transfer function
measurements conducted on 3.5 kW prototypes, were a useful starting point for
current-loop design in a multi-module prototype.

4. Average modeling and modulation scheme development for a Quasi-Single

Stage ZVZCS Three-Phase Buck Rectifier. Chapter 5 illustrates versatility of

7
the modeling procedure when dealing with interconnection issues in this special
multi-converter structure. It is formed by cascading a three-phase buck rectifier
and the ZVZCS converter in the previews chapter. Physical insight provided by
the average circuit model developed for this three-phase rectifier, which is also a
new result, helped to discover the main causes of strong nonlinear relationships
between commanded duty-cycles and effective duty cycles, i.e. voltage transfer
ratio, near the boundaries of the sixty-degree electrical sectors in standard space
vector modulation (SVM). These nonlinearities induced high distortion and ripple
in ac input currents and dc output voltage, which rendered the system unsuitable
for the intended telecommunications application. Physical insight from the model
also helped to develop a new simple and effective modified SVM with feed-
forward duty-cycle compensation scheme that reliably minimizes current
distortion and voltage ripple while keeping the same single dimension control.

8
2. MATHEMATICAL DESCRIPTION OF SWITCHING
POWER CONVERTERS AND THEIR LARGE AND
SMALL-SIGNAL MODELING

This chapter starts with a review of state-space descriptions for PWM converters
in continuous and discrete time forms followed by an outline of small-signal model
derivation in both time forms. Afterwards variations of the method of generalized
averaging are introduced. In addition the approaches to synthesize averaged circuit model
for PWM converters are also discussed and a comparison analysis of these methods is
presented. Then a new modeling procedure to obtain autonomous averaged circuits of
PWM converters is outlined and illustrated through its application to the buck converter.
The resulting averaged circuit covers a wide range of operation, i.e. DCM-CCM.

2.1 Characteristics and State-Space Description of PWM Converters

The PWM converters considered in this work consist of linear resistive and
reactive elements, piece-wise linear switching elements with the externally controlled
ones activated at a constant frequency, and input and output power terminals that can
exhibit ac or dc variables as depicted in Fig. 2.1.

2.1.1. Continuous-time state-space equations

The conditions imposed upon the elements of the power stage allow the
converters to be described, in between certain switching instants tk,i, by linear time-
invariant ordinary differential equations of the form [V4]

d x(t) = A ⋅ x(t) + B ⋅ u( t ) t k ,i −1 < t ≤ t k ,i , (2.1)

k ,i k ,i
dt
where state vector x(t) is n x 1, state transition matrix Ak,i is n x n, input matrix Bk.i is
n x r and input vector u(t) is r x 1.
Switching instants tk,i are determined by combinations of control parameters
and/or state variables from the power stage and control circuitry. Subscript k corresponds
to switching cycle, whose duration is assumed constant and designated by Ts, and
subscript i corresponds to a time interval within each cycle during which the system
maintains the same switch configuration, Fig. 2.3. Entries for matrices Ak,i and Bk.i
depend upon switch conditions (on or off), which determine circuit structure in between
switching instants, and component values. The combinations that determine the switching
instants in the k-th cycle can be described by the set on m constraints

c( x(t k ), p(t k ), u( t k )) = 0 , (2.2)

where p(tk) is a q x 1 vector of independent controlling parameters.

9
 POWER STAGE
SOURCE LOAD
(DC/AC) (DC/AC)

CONTROL

Fig. 2.1. PWM converter structure.

10
2.1.2. Sample-data state-space equations

In general the change on the converter state-space vector x(t) over one switching
cycle, i.e. from tk to tk+1, can be expressed by the n sampled-data relations

x(t k +1 ) = f ( x(t k ), p(t k ), u( t k )) , (2.3)

upon integration of (2.1). f ( . , . , . ) represents a vector valued nonlinear function that in

our case can be simplified to [V3, V4]

x(t k +1 ) = F ( p(t k ) ) ⋅ x(t k ) + H ( p(t k ), u( t k )) , (2.4)

where F (.) and H (.) are n x n and n x 1 matrices respectively that involve matrix
exponentials of Ak,i and are easily computable in terms of Ak,i, Bk,i and u(t).

When a dc-dc PWM converter is operating in steady state the state space vector
returns at the end of the switching cycle to the same value it had at the beginning of it, i.e.

x(t k +1 ) = x(t k ) = F ( p(t k ) ) ⋅ x(t k ) + H ( p(t k ), u( t k )) = X (2.5)

is a constant as well as p(tk)=P and u(tk)=U. As a result (2.2) and (2.5) become

c( X , P ,U ) = 0 (2.6)

and

X = F ( P ) ⋅ X + H ( P ,U ) . (2.7)

Small-signal dynamics of perturbations around an orbit can now be obtained by

keeping up to linear terms of the Taylor series expansion of equations (2.6) and (2.7), i.e.

∆x(t k +1 ) = F ( P + ∆p(t k ) ) ⋅ ( X + ∆x(t k ) ) + H ( P + ∆p(t k ),

(2.8)
U + ∆u(t k ) ) − X

and

c( X + ∆x(tk ), P + ∆p(tk ),U + ∆u(tk ) ) = 0 , (2.9)

where ∆x and ∆p represent those perturbations.

After carrying out some cancellations on the series expansions one obtains:

11
 ∆x(t k +1 ) = F ( P ) ⋅ ∆x(t k ) + ∂ F ( P ) ⋅ ∆p(t k ) ⋅ X
∂p
(2.10)
+ ∂ H ( P ,U ) ⋅ ∆p(t k ) + ∂ H ( P ,U ) ⋅ ∆u(t k )
∂p ∂u

and

∂ c( X , P ,U ) ⋅ ∆x(t ) + ∂ c( X , P ,U ) ⋅ ∆p(t )
∂x k
∂p k

(2.11)
+ ∂ c( X , P ,U ) ⋅ ∆u(tk ) = 0.
∂u

which are basically a discrete small-signal model in implicit form and almost always
needs to be solved numerically to compute the desired discrete transfer functions. Their
continuous-time counterparts can then be computed numerically.

2.1.3 Sampled-data modeling of a simple PWM converter

Since this modeling process gets very involved for high-order systems, some
simplifications based on practical converter characteristics are usually possible. To
illustrate this process, the large-signal sampled-data model for the simple buck PWM
converter, shown in Fig. 2.2, with the so-called peak current control and in CCM of
operation is developed. In this system, in CCM operation, there are two state variables,
inductor current and capacitor voltage, i.e.

x(t) = [i L vC ] ,
T
(2.12)

and the two switching configurations (circuit topologies), depicted in Fig. 2.3, i.e. interval
subscript i in (2.1) takes the values 1 and 2. These switching configurations are
determined by the conduction state of the switch, i.e. on or off, and give origin to matrices
Ak,i and Bk,i,

T
 0 −1 L 
Ak ,1 = Ak ,2 = A=  , (2.13)
1 C 1 R ⋅ C 

1 L 
Bk ,1 =   , (2.14)
 0 

and

12
 0 
Bk ,2 =   . (2.15)
0 

The remaining term in (2.1), input vector at ime tk, is given by

u (tk ) = vi (tk ) . (2.16)

Duration of the first interval in transient regime is determined from conditions

represented in Fig. 2.4 where inductor current waveform, modulating ramp and current
reference are shown. From Fig. 2.4 the switching constraint that determines dk (the duty
ratio for interval i=1) is calculated as

i* ( t k ) − mr ⋅ d k ⋅ Ts = iL ( t k ) + m1 ⋅ d k ⋅ Ts , (2.17)

*
where i ( tk ) represents inductor current reference (independent control parameter p(tk)
in (2.2)), iL ( tk ) is the inductor current values at time tk, mr and m1 correspond to
modulating ramp slope and approximated inductor current slope during interval 1
respectively when capacitor voltage is assumed constant over one switching cycle, i.e. Ts.

The large signal sampled-data model for the buck converter, after assumption of
constant control during each interval can be described as

x(t k + d k ⋅ Ts ) = F1(d k ) ⋅ x(t k ) + H 1(d k ) ⋅ u(t k ) (2.18)

and

x(t k + Ts ) = F2 ( d k ) ⋅ x(t k + d k ⋅ Ts ) + H 2 ( d k ) ⋅ u(t k + d k ⋅ Ts ) , (2.19)

where

A1⋅d k ⋅Ts d k ⋅Ts A1 ⋅σ

F1 ( d k ) = e ∫
, H 1( d k ) = o e ⋅ B1 ⋅ dσ (2.20)

and
A2 ⋅( 1−d k )⋅Ts ( 1− d k )⋅Ts A2 ⋅σ
F2 ( d k ) = e , H 2 ( dk ) = ∫ e ⋅ B2 ⋅ dσ . (2.21)
o

13
 S
L

vi C R

iL
Gate vG

i ∗Ref ∑ Comp

Ramp

Fig. 2.2 Simple buck PWM converter with current feedback.

14
 ON-state OFF-state

S S L
L

15
Vi D C R Vi D C R

Interval i=1 Interval i=2

t k < t < tk + d k TS t k + d k TS < t < t k +1

Fig.2.3. Buck converter circuit topologies

 Interval i=1 Interval i=2 Interval i=1 Interval i=2

VG On Off On Off

i*
mr
ramp
iL
m1 m2

iS

vD

t
vC

tk tk+[Link] tk+1 tk+1+dk+[Link]

TS

Fig. 2.4 Relevant waveforms for duty-cycle calculation

16
Concatenation of (2.28) and (2.19) provides a cycle-to-cycle representation of the system
that can describe the behavior either at the beginning of the cycles, (2.22), or at the
switching instants, (2.23).

x (tk + 1 ) = F2 ( d k ) ⋅ F1( d k ) ⋅ x(tk ) + ( F2 ( d k ) ⋅ H 1( d k ) +

(2.22)
H 2 ( d k )) ⋅ u(tk ).

x (tk + 1 + d k ⋅ Ts ) = F1( d k ) ⋅ F2 ( d k ) ⋅ x(tk + d k ⋅ Ts ) +

(2.23)
( F2 ( d k ) ⋅ H 1( d k ) + H 2 ( d k )) ⋅ u(tk + d k ⋅ Ts ).

When control signals vary slowly as compared to switching period, the matrix
exponentials can be approximated by keeping up to the linear terms in their series
expansion. That is,

Ai ⋅σ
Fi = e ≈ I + Ai ⋅ σ , (2.24)

and

A j ⋅σ A ⋅λ
F j Fi = e e i
≈ I + A j ⋅ σ + Ai ⋅ λ , (2.25)

which are the same approximations made in the continuous-time state-space averaged
method.

After using these approximations in (2.22) the large-signal model becomes

x (t k +1 ) = Φ( d k ) ⋅ x(t k ) + Ψ ( d k ) ⋅ u(t k ) (2.26)

where

Φ (d k ) = I + A1 ⋅ d k ⋅ TS + A2 ⋅ (1 − d k ⋅ TS ) = I + A ⋅ TS (2.27)

17
and

Ψ (d k ) = ( I + A ⋅ TS ) ⋅ B1 ⋅ d k ⋅ TS . (2.28)

Linearization of (2.26), leads to an approximate discrete small-signal model of the

following form

∆ x (tk +1 ) = Φ( d k ) ⋅ ∆ x(tk ) + ( I + A ⋅ TS ) ⋅ B1 ⋅ TS ⋅ u( tk ) ⋅ ∆ d k +
(2.27)
Ψ ( d k ) ⋅ ∆ u(tk ).

Similarly linearization of (2.17) provides ∆ d k as

∆ d k = −∆ iL ( tk ) /( m1 + mr ) ⋅ Ts + ∆ i* ( tk ) /( m1 + mr ) ⋅ Ts , (2.28)

which when substituted in (2.27) gives after some manipulations the final form

∆ x (tk + 1 ) = Κ ⋅ ∆ x(tk ) + Λ ⋅ ∆ i* ( tk ) + Μ ⋅ ∆ vin(tk ) . (2.29)

Equations 2.12 through 2.27 show that large and small-signal sampled-data model
can be easily and systematically obtained for simple PWM converters in open and closed
loop operation. Unfortunately modeling of interconnected converters from their
independent models is not a straightforward procedure and most of the time requires a
complete new derivation.

2.2. Generalized Method of Averaging for PWM Converters

The main objective for applying the generalized method of averaging, also known
as KBM (Krilov, Bogoliubov, Mitropolski), to time varying systems, such as PWM
converters, is to obtain an autonomous model that closely describes a moving average of
the variables in the original system. In other words, we are trying to derive a simpler
model that retains some of the main properties, a slow dynamics manifold, of the initial
system.

18
 In this chapter a general description of this method following the lines in [K5] and
how to apply it to a simple PWM converter in CCM are presented. A simple way to
estimate information about ripple of the variables is also discussed.

2.2.1. Procedures of the method

In order to apply the KBM method to a system it is necessary to cast it in the

standard form

d
x( t ) = ε ⋅ F ( t , x ), x( t 0 ) = x 0 , (2.30)
dt
where ε is a small non-dimensional parameter and F is a vector valued function (see K5
and the references within for a rigorous justification of averaging for (2.30)). The
integral

1 T
T →∞ T ∫ 0
G( ⋅ ) = lim F ( s ,⋅ )ds , (2.32)

is defined as the time average of (2.30) and leads to the new time-invariant averaged
model

y (t ) = ε ⋅ G( y ), y( t0 ) = y0 . (2.33)

When the system is periodic or quasi-periodic, as in PWM converters, the integral

in (2.32) is finite and hence the limit exists.

The KBM method is based on the change of variables

x (t ) = y( t ) + ε ⋅ ψ 1 ( t , y ) + ε 2 ⋅ ψ 2 ( t , y ) + ε 2 ⋅ ψ 3 ( t , y ) + ... , (2.34)

where ψ i are functions of time with zero-average value, which transforms the original
system, i.e (2.30), into the time invariant system

19
 d
y (t ) = ε ⋅ G1 ( y ) + ε 2 ⋅ G 2 ( y ) + ε 3 ⋅ G3 ( y ) + ... . (2.35)
dt

In order to obtain a set of equations in the new variable y, (2.30), (2.34) and (2.35)
need be used. First, (2.34) gets differentiated with respect to time, then (2.30) is used to
eliminate x& , (2.35) to eliminate y& , and (2.34) to eliminate x. Then terms with the same
power of ε are equated to get a system of equations that can be sequentially solved for
ψ i ( t , y ) and G i ( t , y ) .

2.2.2. Illustration of the generalized method of averaging for a simple PWM

converter

This process is presented here for single switch PWM converters in CCM operation, i.e.
two intervals per switching cycle. In the next section the same process will be specifically
used with the open loop buck converter.

Equation 2.30 can be written as

d x(t) = [ A + h( t ,T ) ⋅ ( A − A )] ⋅ x(t)
2 s 1 2
dt (2.36)
+ [ B 2 + h( t ,Ts ) ⋅ ( B1 − B2 )] ⋅ u( t )

where matrices Ai and Bi correspond to those defined in (2.1) for intervals 1 and 2 after
dropping the index k, and

h( t ,Ts ) = H [ d ( t ) − ramp ( t ,Ts )] . (2.37)

where H(z) is the Heaviside or unit step function, d(t) is the duty-cycle control signal and
the function ramp(t,TS) corresponds to the PWM modulating signal. The latter is
described by using the module operation

t mod( Ts )
ramp ( t ,Ts ) = . (2.38)
Ts

Calculation of the parameter ε is performed by selecting the largest absolute

value of the entries in matrices Ai and Bi, designated by ξ in (2.39), and multiplying it
by Ts, i.e.

20
 ε = max
i,j
{ ai , j , bi , j }⋅ T s = ξ ⋅ Ts . (2.39)

If time is scaled as

t = Ts ⋅ τ , (2.40)

equations (2.36) and (2.37) can be expressed in terms of ε and τ as

d x(τ) = ε ⋅ { [ 1 ⋅ A + h( τ ,1 ) ⋅ ( A − A )] ⋅ x( τ)
dτ ξ 2 ξ 1 2

(2.41)
1 h( τ ,1 )
+ [ ⋅ B2 + ⋅ ( B1 − B2 )] ⋅ u( τ )}
ξ ξ

and

h( τ ,1 ) = H [ d ( τ ) − ramp ( τ ,1 )] (2.42)

respectively. Thus application of the averaging operator (2.32) to the right hand side
(RHS) of (2.41) produces

1 d
G(y) = [ ⋅ A2 + ⋅ ( A1 − A2 )] ⋅ y
ξ ξ
(2.43)
1 d
+ ⋅ [ B2 + ⋅ ( B1 − B2 )] ⋅ U ,
ξ ξ

where d is the average duty-cycle. The average model, after returning to the original time
scale, is given by

d
y( t) = [ A2 + d ⋅ ( A1 − A1 )] ⋅ y( t )
dt (2.44)
+ [ B 2 + d ⋅ ( B1 − B2 )] ⋅ U ,

which is the same result obtained through state-space averaging. Estimates of variables
ripple can now be computed by continuing with the KBM method. Manipulation of
(2.34), (2.35) and (2.43) leads to

21
 h( τ )
⋅ ( A1 − A2 ) ⋅ [ y + ε ⋅ ψ 1 + ε 2 ⋅ ψ 2 + ...]
1 
ε ⋅  ⋅ A2 +
ξ ξ 
1 h( τ ) 
+ ε ⋅  ⋅ B2 + ⋅ (B1 − B2 )
ξ ξ 
(
= ε ⋅ G1 + ε 2 ⋅ G 2 + ε 3 ⋅ G3 + ... ) (2.45)
 ∂ψ ∂ψ 1
+ε ⋅ 1 + ( 
⋅ ε ⋅ G1 + ε 2 ⋅ G 2 + ...  )
 ∂τ ∂τ 
 ∂ψ ∂ψ 2
+ε2 ⋅ 2 + ( 
⋅ ε ⋅ G1 + ε 2 ⋅ G 2 + ...  ... , )
 ∂τ ∂τ 

from where equating terms with the same power of ε gives

1 h( τ )  1 h( τ ) 
ε: ξ ⋅ A + ⋅ ( A − A ) ⋅ y + ξ ⋅ B + ⋅ ( B − B )

2
ξ 1 2
 
2
ξ 1 2

(2.46)
∂ψ 1
= G1 + ,
∂τ

1 h( τ )  ∂ψ 1 ∂ψ 2
ε2 : ξ ⋅ A + ⋅ ( A − A ) ⋅ ψ = G + ⋅ G + , (2.47)

2
ξ 1 2

1 2
∂τ
1
∂τ

1 h( τ )  ∂ψ 1 ∂ψ 2 ∂ψ 3
ε2 : ξ ⋅ A1 + ξ ⋅ ( A1 − A2 ) ⋅ ψ 2 = G3 + ∂τ ⋅ G 2 + ∂τ ⋅ G1 + ∂τ .(2.48)
 

Equation (2.46) is used to solve for G1 by taking the average over one period with respect
to τ and the result is the same as the RHS of (2.44). Now G1 is substituted in (2.46) and
then the constant of integration is selected to make ψ 1 zero-average and of period Ts.
Similarly the other functions can be calculated to obtain a higher order approximation for
variables ripple (see [K5] for modeling of the boost converter and its ripple estimation).

22
2.2.3. Generalized method of averaging for the open loop buck converter

The converter in Fig.2.3 is considered here but in open loop and its continuous-
time state-space equations, i.e. (2.36), after substituting (2.13)-(2.15) reduces to

d x(t) = A ⋅ x(t) + h( t ,T ) ⋅ B ⋅ v ( t ) , (2.49)

1 s 1 in
dt

and

h( t ,Ts ) = H [ d − ramp ( t ,Ts )] . (2.50)

The average equation is then given by

d y(t) = A ⋅ y(t) + d ⋅ B ⋅ v ( t ) (2.51)

1 1 in
dt

and (2.45) reduces to

1 h( τ ) ∂ψ 1
⋅ A1 ⋅ y + ⋅ B1 = G1 + , (2.52)
ξ ξ ∂τ

from where after some manipulations ψ 1 is obtained as

ψ1 (τ ) =
1
ξ
 1
( ) 
⋅ B1 [h( τ ) − d ]⋅ ramp (t ,1) + [1 − h( τ )]⋅ d + ⋅ d 2 − d  (2.47)
2
 

and the remaining Gi for i=2, 3, … are zero.

23
2.3. Averaging Method for Two-Time Scale PWM Converters
Most PWM converters can be classified as one or two-time scale systems. A
method for the latter, developed very similarly by different authors [N2, S13, W3], is
presented here. The former are already covered by the method in section 2.2.

2.3.1. State-space description for two-time scale PWM converters

The two-time scale characteristics of a PWM converter can be explicitly shown

by representing the system in the form

d
x (t ) = ε ⋅ f ( t , x , y ), x( t 0 ) = x 0 , (2.48)
dt

d
y (t ) = g( t , x , y ), y( t 0 ) = y 0 , (2.49)
dt

where ε is again a small non-dimensional parameter, x and y are state vectors of

dimension n and m respectively, and f and g are vector valued functions.

The average model for (2.48) is defined as

d
X (t ) = ε ⋅ f 0 ( X ), X ( t 0 ) = x0 , (2.50)
dt
with

1 t +Ts
f 0 ( x ) = lim ∫t f (τ , x , φ(τ , x , t ′, y0 )) dτ , t ≥ t0 , (2.51)
Ts → ∞ T
s

where φ(τ , x , t ′, y0 ) is the solution of (2.49) with initial value y (t ′) = y0 and fixed x.

24
When x is fixed switch patterns in PWM converters do not change, and hence, if
φ(τ , x , t ′, y0 ) converges to a periodic function ψ (τ , x ) in a finite time (2.51) can be
simplified to

1 Ts
f0 ( x ) =
Ts ∫ 0 f (τ , x ,ψ (τ , x )) dτ , (2.52)

whose value is finite as described in section 2.2. Thus ψ (τ , X ) becomes the steady-state
solution of y (t) for fixed X.

For PWM converters (2.48) and (2.49) can be written as

dx
= Aisx ⋅ x + Aisy ⋅ y + Bis ⋅ u , (2.53)
dt

dy
= Ai fx ⋅ x + Ai fy ⋅ y + Bi f ⋅ u , (2.54)
dt

where superscripts s and f stand for slow and fast in Ai and Bi matrices, which are
constant during interval i.

2.3.2. Practical procedure for the method

Starting with the PWM converter equations in the form of (2.53) and (2.54) the
following steps summarize the averaging procedure.

1. Assume slow variables x as fixed in the equations for fast variables y, (2.54):

dy
dt
{
= Ai fy ⋅ y + Ai fx ⋅ X + Bi f ⋅ u . } (2.55)

25
2. Compute steady-state solution yss of fast variables in (2.55);

3. Substitute yss into (2.53) to get

dx
= Aisx ⋅ x + Aisy ⋅ y ss + Bis ⋅ u . (2.57)
dt

3. Compute the average of (2.57), over one switching period,

{A }
r
1 t k ,i
f0 ( x ) =
Ts
∑∫t
i =1 k ,i −1
i
sx
⋅ x + Aisy ⋅ y ss + Bis ⋅ u dt , (2.58)

to obtain the average model

dX
= f0 ( X ) . (2.59)
dt

2.4. Synthesis Method for Averaged Circuit Models of PWM Converters

Development of autonomous averaged and small-signal circuit models according

to [S4, V8] is presented in this section. Their intent is to reproduce state-space averaging
results for single switch PWM converters. In [S4], an in-place circuit averaging is
performed and analytical support is given whereas in [V8] an equivalent 3-terminal
circuit is sought for the so-called PWM switch.

2.4.1. In-place averaging

When the moving average operation over one switching cycle given by

26
 1 t
y( t ) =
TS ∫t −T y(σ ) dσ
S
(2.60)

is applied, in-place to each branch variable of PWM converters, in steady state operation,
the transformed branch variables satisfy the same node and mesh constraints as the
original variables. Therefore the synthesis of an averaged circuit model can be oriented
towards a circuit layout topologically equivalent to the original simple PWM converter.
Since a requirement for linear reactive elements not to be altered by the moving average
operator is that the latter and differentiation with respect to time commute, i.e.

d   1
[ y( t )] = d  1
t

dt dt  Ts ∫ t −Ts y(σ ) dσ  = T [y(t ) − y(t − T )]

s
s

(2.61)
1 t d d 
=
Ts ∫ t −Ts dσ y(σ ) dσ =  dt y( t ) ,

which implies continuous differentiability for the state variables, i.e. their first time
derivative to be continuous. Unfortunately this is not the case for the PWM converters
treated here as stated by (2.1) and hence the moving average of the state variables do no
satisfy the converter’s state equations in general.

Application of the one cycle moving average operator in (2.60) to the state-space
representation of the PWM converter in (2.1), and reproduced here for clarity,

d x(t) = A ⋅ x(t) + B ⋅ u( t ) t k ,i −1 < t ≤ t k ,i , (2.62)

k ,i k ,i
dt

leads to the form

d x(t) =
dt
1 t (2.63)
[Ak ,i ⋅ x(s) + Bk ,i ⋅ u( s )]⋅[H ( s − t k ,i−1 ) − H ( s − t k ,i )] ds ,
Ts ∫ t −Ts

27
which is valid for all k,i since H( .), the Heaviside step function, in the last bracket selects
the appropriate time intervals for matrices Ak,i and Bk.i.

Direct computation of this moving average would require keeping track of

intervals within each switching cycle, which is a terrible burden. Instead an approximated
average per switching cycle described by

d X(t) =
dt
1 (2.64)
∫ t −T [A k ,i ⋅ x(s) + Bk ,i ⋅ u( s )]⋅[H ( s − t k ,i − 1 ) − H ( s − t k ,i )] ds
tk

Ts k s

is used, where X is the new averaged state and tk =t. In other words the moving average
interval of width Ts and the switching cycle are assumed to coincide.

[S4] provides a theorem regarding the synthesis of an averaged circuit for a PWM
converter with a single controlled and linear time invariant components. The converter
must fulfill the following conditions:

(a) be partitioned as shown in Fig. 2.5,

(b) have unique solutions for voltage and currents of its branches, e.g. no
capacitor-voltage source loop, etc.,

(c) have a hybrid representation for the RESISTORS multiport in Fig. 2.5 with
controlling port variables taken as currents for those ports connected to
current source or inductive ports and as voltage for those ports connected
to voltage source or capacitive ports, with a single current-controlled
switch port and a single voltage controlled switch port.

Given all this it is possible to obtain an averaged circuit model by replacing the
two-port switch network with a resistive two-port whose hybrid representation is

d
H S (d ) = ⋅ H 22 , (2.65)
1− d

for d ≠ 1 , where H22 is the hybrid immittance seen by the switch two-port when all
current source and inductive branches are replaced by open circuits and all voltage source
and capacitor branches are replaced by short circuits.

28
 Since application of this theorem is restricted to single switch converters, a
procedure introduced in [V8] for the PWM-switch and then complemented in [L11, X4,
Y2], which also leads, in a more direct way, to the synthesis of a valid circuit for the
same hybrid representation is shown instead.

2.4.2. PWM-switch equivalent circuits

This method was proposed in [V8] for dc and small-signal model. It starts by
noting that simple PWM converters include one active switch (externally controlled
device) and one passive switch (diode). The combination of these two switches, shown in
Fig. 2.6(a), is the so-called PWM switch. Because at most one switch is conducting at a
time, some relationships for the instantaneous terminal variables of the PWM switch,
depicted in Figs. 2.6(b) remain invariant in simple PWM converters, i.e.

i ( t ) ; 0 ≤ t ≤ d ⋅ Ts
ia ( t ) =  c (2.66)
 0 ; d ⋅ Ts ≤ t ≤ Ts

and

v ( t ) ; 0 ≤ t ≤ d ⋅ Ts
vcp ( t ) =  ap , (2.67)
 0 ; d ⋅ Ts ≤ t ≤ Ts

where i and v represent instantaneous port variables, subscripts a, p, c stand for active,
passive and common respectively, and [Link] represents the interval within the switching
cycle when the active switch is on. From here an average model for the PWM switch,
valid in steady-state operation, i.e. fixed duty-ratio, is developed by computing, from the
waveforms in Fig. 2.6(b), average current and average voltage at its terminals. That is,

Ia = d ⋅ Ic (2.68)

and
Vcp = d ⋅ ( Vap − I c ⋅ req ⋅ ( 1 − d )) , (2.69)

where I, V and d represent average quantities and req is the equivalent resistor that causes
the jump in vap . That equivalent resistor is usually a combination of capacitor equivalent
series resistor (esr) and/or load resistor. For instance in the boost and buck-boost
converters re is the parallel combination of output filter capacitor’s esr and load resistor.

29
 An equivalent circuits for the average model of the PWM switch, i.e. (2.68) and
(2.69), is shown in Fig. 2.7. [V8] uses an ideal transformer instead of the controlled
sources. Note that the circuit representation for the PWM switch is not unique but must
have the same terminal variables relations. The small-signal model of the PWM switch
can be obtained by linearizing equations (2.68) and (2.69). The final result [V8] is

∆ ia = d ⋅ ∆ ic + I c ⋅ ∆ d , (2.69)

∆ vap ∆d
∆ vap = + ∆ ic ⋅ req ⋅ ( 1 − d ) − [ Vap + I c ⋅ ( 2 ⋅ d − 1 ) ⋅ req ] ⋅ . (2.70)
d d

Computation of typical transfer functions such as control or input voltage to either

state variables or output voltage can be carried out by placing the small-signal PWM
model into the converter and then using node and mesh equations.

DCM of operation is covered in [V8] for the same type of analysis. Similar works
in [X4, Y2] cover DCM and CCM operation respectively. Instead of transformer and
equivalent resistor to replace the switch-diode pair the models exhibit a controlled current
source and a controlled voltage source. The latter represents average switch current
whereas the former represents average diode voltage. In [L11] a simplified version of
[Y2], no capacitor esr included, is used to model simple PWM converters with a current
feedback loop.

2.5. Analysis of Strengths and Weaknesses of these Methods

Of all these methods for switching power converters generalized averaging

(KBM) is the most systematic, can include any type of feedback loops but provides very
little physical insight and becomes almost untraceable for high order systems. Even
though state variables’ ripple can be approximated to an arbitrary degree it requires
keeping track of phase relationships between PWM modulating signal perturbations in
control and input signals. In other words time varying effects must be considered, which
conflicts with the main purpose of averaging, i.e. obtaining an autonomous
representation.

Physical insight is incorporated into two-time scale averaging for switching power
converters with the classification of fast/slow state variables based on waveforms
analysis. Moreover the procedure for this method of averaging is systematic and can
handle PWM as well as several resonant converter types. Unfortunately energy holding

30
 i

v 1
REACTIVES RESISTORS

SWITCH

SOURCES

Fig. 2.5. Partition of PWM converter structure.

31
 Ic
ia(t )
current port ic(t )
Ia
0 0

ia (t ) d ic (t )
a
Vap
c

32
vap(t ) vcp(t )
1-d
Vap − IC req (1−d)
vap(t ) vcp( t ) Vcp

current port
0 0

voltage port
Ts Ts
p
d Ts d Ts

a) Structure and terminal variables a) Terminal waveforms

Fig.2.6. The PWM switch

 (1 − d) ⋅ d ⋅ re
a c

ia ( t ) ic ( t )
d ⋅ ic (t) d ⋅ v ap ( t )

Fig. [Link]-switch equivalent average circuit.

33
elements, dealt with in more detail in Chapter 4, are not allowed within the fast state
variables and steady-state conditions are used in some portions of the procedure. These
steady-state conditions lead to unaccounted dynamic characteristics, g.e. input, control
and ripple induced effects, which constrain model ranges, g.e. order, bandwidth.

PWM switch models and their extensions to some types of resonant converters
give very good physical insight and allow for straightforward dc and ac calculations
through circuit analysis tools. However, constraints imposed on the switch-diode pair
configuration limit the set of converters that can be modeled.

In-place circuit averaging preserves converter structure and hence provides strong
physical insight. In addition a systematic and rigorous procedure leads to analytical
hybrid representation for the switch-diode pair. Regrettably, this procedure can become
very involved for high order systems and deals with CCM and DCM separately as it is
also the case for all previous methods. Even though PWM switch modeling and its
extensions deal with multiple switches in a systematic way there is no provision for full-
bridge based converters or energy storage elements.

2.6. A New Procedure for Averaged Circuit Models

Strong features from some of the methods discussed above are complemented
with analog simulation and series expansion practices as well as heuristic guidelines to
form a new modeling procedure. A simplified version of the so-called duo-mode average
model [R5] that covers DCM and CCM for the buck converter with current feedback loop
is developed to illustrate the new procedure and then simulation results from switching
and average models are presented.

2.6.1. Philosophy of the new average modeling procedure

Representation of port characteristics, e.g. impedances, average variables, as well

as transfer characteristics, e.g. voltage conversion ratio, will be the major property sought
for the average circuit model.

The starting point for the procedure is the set of open-loop typical waveforms in
transient regime and of switching structures through which the converter passes, Fig. 2.8.
Inclusion of transient regime conditions overcomes limitations induced by steady-state
conditions used in PWM-switch modeling and in two-time scale averaging methods.
Then classification of state variables into fast and slow types from the two-time scale
method is used together with circuit topologies and typical waveforms to select, at input
and output ports, filtering networks (slow state variable components) whose structures do
not get altered by switch transitions, i.e. linear time invariant (LTI) networks, so that their
contributions to open-loop input/output characteristics (impedances, dynamics) are
preserved.

34
 To keep consistency with this goal the equivalent driving and/or loading
controlled sources for those LTI filtering networks must be identified and their moving
average should be efficiently and accurately approximated (for this task one-cycle
average has been heuristically selected). In other words we are trying to mimic the
moving average properties stated in (2.61), from in-place averaging section, by applying
the one-cycle average of those controlled sources to the LTI networks in the previous
paragraph.

At this stage feedback loop effects, e.g. algebraic and dynamic constraints, can be
incorporated for stability and transient analysis, and finally a simulator specific
implementation should be developed.

In order to help with application of the procedure it gets described in a step-by-

step fashion together with guidelines in the next section.

2.6.2. Steps of the new average modeling procedure and their guidelines

Step 1: Classify state variables according to slow/fast dynamics with respect to switching
frequency and select meaningful slow states for average circuit model. These states
should have neither zero steady-state average nor a zero value during a significant
amount of time within the switching cycle and their moving average main frequency
components should be much lower than the switching frequency, Fig. 2.9.

Step 2: Select linear time invariant (LTI) input and output parts, i.e. sub-networks made
of sources and passive components whose structures do not get altered by switch and
diode transitions, Fig. 2.10.

Step 3: Identify “dependent” variable(s) drawn from input network(s) and “independent”
variable(s) delivered to output network(s), all from the Step 2, to be represented as
controlled sources. These variables should not create discontinuities in state variables
regardless of initial conditions, i.e. no current sources in series with inductors or voltage
sources in parallel with capacitors, Fig. 2.11.

Step 4: Derive expression for one-cycle average of controlled sources in Step 4 from
typical waveforms and circuit topologies. In most cases a few low order terms of power
series approximation for waveform description will suffice, Fig. 2.12.

Step 5: Derive algebraic constraints in transient regime, e.g. variable-state dependent

switching instants, DCM-CCM boundary conditions; as a function of input, control and
fast dynamics variables. The latter should not be related to an energy holding component,
described in detail in Chapter 4, since its state variable contributes with a dynamic
constraint, i.e. an additional state, which usually requires a particular treatment. Here also
low order terms in power series approximation of waveforms may suffice, Fig. 2.13.

Step 6: Incorporate feedback-loop induced algebraic constraints and additional estates

(e.g. control and state dependent switching instants, compensator own states). By starting

35
with an open loop system and later including feedback loops effects it is very likely that
only this step will need modifications when changing control strategies, Fig. 2.14.

Step 7: Use common and reliable analog simulation practices to implement the average
model in circuit simulators and to blend models for different operating modes (e.g.
closing a loop around an operational amplifier to find zeros or the inverse of a function,
manipulating equations to avoid undefined operations such a division by zero, detecting
inadmissible variable values such as bipolar output from a rectifier, on the fly state
variables removal/addition etc.), Fig. 2.15.

2.6.3. Application of the new procedure to the buck converter

Figures 2.2, 2.3 and 2.4 show the buck converter with current feedback loop, its
circuit topologies and its typical waveforms respectively in CCM. Fig. 2.16(a) exhibits an
averaged circuit model for the same converter, which can be derived by applying the new
procedure as detailed next

Classification of state variables in Step1, according to their dynamics speed,

labels inductor current iL and capacitor voltage vC, shown in Figs. 2.4 and 2.9, as slow
type. In Step 2 the voltage source gets easily identified as linear time invariant input
structure whereas the second order filter becomes the output side counterpart, Fig. 2.10.

Step 3 identifies switch current and diode voltage as “dependent” variable drawn
from LTI input part and “independent” variable delivered to LTI output part in the
previous step, Figs. 2.8 and 2.11.

In Step 4 the one-cycle average both for switch current iS and diode voltage vD ,
in Figs. 2.8 and 2.12 are calculated as

iS = d ⋅ iL (2.71)

and

vD = d ⋅ vin . (2.72)

where d , iL and vi are duty-ratio command, average filter inductor current and input
voltage respectively.

From Fig. 2.8 peak and average inductor current, i pk and iL are related up to a
first order approximation by

i pk = i L +
1
2
[ ]
∆ iup ⋅ d + ∆ i dwn ⋅ (1 − d ) , (2.73)

36
where

(vi − vC )
∆ iup = m1 ⋅ d ⋅ Ts = ⋅ d ⋅ Ts , (2.74)
L

and

vc
∆ idwn = m2 ⋅ (1 − d ) ⋅ Ts = ⋅ ( 1 − d ) ⋅ Ts . (2.75)
L

For later use d2 is defined as

i pk
d2 = . (2.76)
m2 ⋅ Ts

Algebraic constraint derived in Step 5 corresponds to CCM-DCM boundary

condition, Fig. 2.1.3. Typical operating waveforms and circuit topologies for the buck
converter in DCM operation are shown in Fig. 2.17. Development details for the average
model in DCM shown in Fig. 2.18 will be presented after completing derivation in CCM .

Step 6 derives the algebraic constraint induced by current feedback loop

incorporation, Fig. 2.14, which determines switching time in terms of current reference
and state variables, i.e.

i* − mr ⋅ d ⋅ TS = i pk (2.76)

Circuit simulator oriented implementation of average model in Step 7, includes

feedback loop around an operational amplifier to find the root (zero) of a function,
Fig. 2.15(a), as well as selection of a root within an admissible interval (duty-cycle
between zero and one) and equation manipulation to avoid zero divisor condition,
Fig. 2.15(b).

Before applying the new modeling procedure to DCM operation a few

observations about the average circuit models for CCM in Fig. 2.16 are included. Even
though Model I is the only one derived so far, it can be transformed into the others
through well-known controlled-source manipulation rules form circuit theory. As a result
all three models exhibit the same input, output and transfer characteristics, and obviously
any one can be transformed into the other two. Note that in Figs. 2.16(b) and (c) the
controlled sources represent in place average voltage or current for the switch or the
diode and are labeled as such.

The papers mentioned in the PWM switch model section replace switch and
diode by average controlled sources and they arrive to average circuit models II and III in
Fig. 2.16. From all of this it is clear that an input-output description of a switching power
converter may have multiple average circuit representations and that sometimes several

37
or even all of them can be generated by a single procedure. However our goal is to have a
modeling procedure that can handle as many types of PWM converters as possible, and
some resonant converters as a byproduct, without trying to derive multiple average model
structures for the same converter.

Figure 2.17 shows circuit topologies and typical waveforms for the buck
converter in DCM operation. The corresponding average model, presented in Fig. 2.18,
can be derived by following the new procedure.

Classification of variables according to their dynamics speed, Step 1, labels

capacitor voltage as the only slow variable since filter inductor current stays at zero
during a significant portion of the switching cycle. Therefore its one-cycle average solely
depends on present switching cycle conditions, i.e. its own dynamic history does not
directly matter.

In Step 2 only output capacitor is selected as the LTI part in that side whereas the
voltage source gets selected for the input counterpart since the filter inductor is ruled out
because of the diode, which by being connected in series with it during the second
interval, prevents the current from becoming negative, i.e. makes the inductor look
nonlinear.

From Step 3 switch current and filter inductor current get respectively identified
as “dependent” variable drawn from the input LTI part and “independent” variable
delivered to the LTI output part.

Calculation of one–cycle average for the variables in Step3 is carried out in Step 4
with help from Fig. 2.17(b) where average switch current is clearly given by

i pk
iS = ⋅d , (2.77)
2

with

i pk = m1 ⋅ d ⋅ TS = m2 ⋅ d 2 ⋅ TS , (2.78)

where d 2 remains consistent with its definition in 2.76. Similarly one-cycle average filter
inductor current is expressed as

i pk
iL = ⋅ (d + d 2 ) , (2.79)
2

which can be combined with 2.74, 2.75 and 2.78 to obtain

38
 iL =
(vi − vC ) ⋅ d 2 ⋅ T v 
⋅  i  . (2.80)
S
2⋅L  vC 

The latter is consistent with the claim that one-cycle average filter inductor current is
completely determined by present cycle conditions and hence classifies as a fast variable.

The CCM-DCM boundary condition, illustrated in Fig. 2.13, leads to the

expression

i pk
iL = (2.81)
2

for which to check during the simulation when both average models, i.e. CCM and DCM
version, get combined below by following the approach called duo-mode model
presented in [R5] and shown in Fig. 2.19(a), which uses an ideal transformer
representation, to cover CCM and DCM operation. Fig. 2.19(b) shows the controlled
source equivalent version of the model. The transformer on the left with turns ratio 1:d
represents CCM operation whereas the other transformer, with turns ratio (d + d 2 ) : 1 ,
makes adjustments for DCM operation. Notice that if the constraint

d2 ≤ 1 − d (2.82)

is enforced after calculating d2, according to (2.76), the turns ratio for the right
transformer reduces to 1:1 during CCM, which makes it irrelevant as far as input-output
transfer characteristics concerns and the correct model is seen. However during DCM
operation d2 must be adjusted to enforce (2.80), i.e. average inductor current. The analog
implementation diagram shown in Fig. 2.21 satisfies both CCM and DCM constraints.

Application of simple controlled-source manipulation practices from network

theory transforms the average circuits in Fig. 2.19 into those in Fig. 2.20 while keeping
the same input-output characteristics and all the relevant information avilable. The model
in Fig. 2.20(b) can be covered by the new procedure if the circuit simulation oriented
implementation in Step 7 is expanded to search for versatile analog circuit representations
that can change the number of state variables (filter inductor current state removed during
DCM) in real time during the simulation in a smooth and reliable fashion, i.e. no
convergence prone or discontinuity inducing structures.

Current feedback loop incorporation in Step 6 deals with (2.76) again but ipk is
now given by (2.78) instead of (2.73). This illustrates another situation with which the
versatile analog circuit representations in the previous paragraph must cope.

Regarding Step 7, Fig. 2.22 shows an analog circuit schematic to implement the
calculation, in real time during the simulation, of d and d2 to allow for smooth transitions
between CCM and DCM .

39
2.6.4. Model verification and comments

Verification of the average model was conducted through Saber simulations.

Schematics and template listings for these simulations are included in Appendix A.

Figure 2.23 shows duty ratios, inductor current and output voltage waveforms
from switch and average model. A zoom-in on these waveforms is shown in Fig. 2.24. It
is apparent that average model waveforms very closely track those moving averages from
the switch model for large transients, both in CCM and DCM operation even when the
converter moves back and forth between those modes.

It is important to point out that there were no convergence problems for the
average model and that waveform tracking was very good for simulation step size more
than one order of magnitude larger than the step used with the switch model.

This close tracking indicates that the average model can be used to predict start-
up transients and feedback loops effects and hence it can help in power stage and control
design.

In these simulations good familiarity with the specific circuit simulator and
reliable simulation practices is a must.

40
 On Off On Off

VG
ON-state

S L i*
mr
ramp
iL
Vi D C R m1 m2 iL

iS

OFF-state

41
S L vD

D C R vC
Vi

dT S
TS

a) Switch structures (circuit topologies) b) Operating waveforms

Fig.2.8. Starting point for new average modeling procedure

 iL Slow vC
Variables

t t

TS TS

42
Fast
t Variables
t

Fig.2.9. Step 1: Slow/fast variables separation

 Power
vi Loadx
LTI LTI
Input Output
Part Part
ii Loadz

Converter

LF

vi CF RLoad

Fig. 2.10. Identification of Linear Time Invariant Input/Output parts.

43
 Power

vi ia vx Loadw
LTI LTI
Input Output
Part Part
ii vb iy Loadz

Converter

44
LF

Internal
vi ia Slow vx CF RLoad
States

Fig.2.11. Step 3: Identification of “dependent” variable drawn from input and

“independent” variable delivered to output LTI parts
 On Off On Off

VG

* iL
iL

iS iS iS = d iL

45
vD vD vin

t
v D = d v in
dT S
TS

a) Dependent and independent waveforms b) One-cycle average

Fig.2.12. Step 4: Calculation of controlled source one-cycle average

 VG
On Off
m 1 d 1 TS = m 2 d 2 TS = i pk

i*
TS

ipk
m2
m1

46
iL (d 1 + d 2 ) i pk
iLf iL = i pk =
2 2
t
[Link] [Link]
tk tk+1

a) Typical waveforms b) Algebraic constraint derivation

Fig.2.13. Step 5: Calculation of algebraic constraints

 On Off On Off

VG

i*
mr
ramp
i * − m r d 1 TS = i pk
iL
m1 m2 iL

47
TS 2 2
iL +
2
[ ]
m 1 d + m 2 (1 − d ) = i pk
dTS
TS

a) Waveforms with feedback loop b) Loop-induced constraint derivation

Fig.2.14. Step 6: Incorporation of feedback loop

 Root interval constraint
through limiter
Zero divisor potential
Out
problem d2
m1 d 1 1-d1
X d2 =
m2 In
Y C
R
f(X,Y) = 0 Known input vector d 2 m2 − d 1 m1 = 0 _
zero OP
+
i pk (d 1 + d 2 ) − 2 i L = 0 C
R
Z = [ i* , i L ,Vin ,Vo ]
C zero
_
zero R i * − m r d 1 Ts − i pk = 0 OP

48
+
_
OP
+ Out
d1
2 iL
i pk = 1
d1 + d 2
In
Zero divisor
potential problem Root interval constraint
through limiter

a) Root finder through loop

around operational amplifier b) Robust treatment of equation and root selection

Fig.2.15. Step 7: implementation of circuit simulator oriented average model

 Lf

iLf
Vi RLoad
iS vD Cf

a) Averaged circuit model I

iS vS

49
Lf Lf

iLf iLf
Vi RLoad Vi RLoad
Cf iD Cf
vD

b) Averaged circuit model II c) Averaged circuit model III

Fig.2.16. Average circuit model for buck converter in CCM operation

 Lf
VG
On Off
iLf
Vi RLoad
Cf
i*
mr
a) Switch on interval ramp
m2
m1
Lf
iLf
iL
iLf
Vi RLoad
Cf

50
iS
b) Diode conducting interval

Lf vD vC v in

iLf=0 t
Vi RLoad dT S d2 TS
Cf
TS

c) Idling interval d) DCM operation waveforms

Fig.2.17. Buck converter in DCM operation

 Lf

Vi iS iL RLoad
Cf

Fig. 2.18. .Average circuit model for buck converter in DCM.

51
 Lf

Vi 1 d d+d2 1 iL RLoad
Cf

a) Transformer based average circuit model

52
Lf
ix iL

iL vx RLoad
vi d ix d vi vx
(d + d 2 ) (d + d 2 ) Cf

b) Controlled-source based average circuit model

Fig.2.19. Average circuit models for buck converter in CCM and DCM operation
 Lf

Vi d + d2 d iL RLoad
Cf

a) Transformer based average circuit model

LF

53
d d iL RLoad
Vi iL vi CF
d + d2 d + d2

b) Controlled-source based average circuit model

Fig.2.20. Input/output structure average circuit models for buck converter in CCM
and DCM operation
 Limiter

Out

d2
1-d

In

i pk
Eqn (2.73)
m2 C
 
d



Eqn (2.75)
d 
 2  R
Y= I  d 2 ⋅ m2 ⋅ Ts − i pk = 0 zero
 Lf 
_
  OP
Vin  +
 
V  Eqn (2.79)
 o 
...

Fig. 2.21. Analog computation of d2.

54
 Limiter

Out
d2
1-d

In

i pk
Eqn (2.73)
m2 C
 * 
i  Eqn (2.75)
 
d2  zero
  R
Z= I  d 2 ⋅ m2 ⋅ Ts − i pk = 0 _
 Lf  OP
v  +
 i 
v 
...

 o  C

i * − mr ⋅ d ⋅ Ts − i pk = 0 zero R
_
+OP

Out
d
1

In

Limiter

Fig. 2.22. Analog computation of d and d2 with feedback loop.

55
 Fig. 2.23. Simulation results from average (red-dashed) and switch (green-
solid) mode. Top: duty ratios, middle: inductor current, bottom: output voltage.

56
 Fig. 2.24. Simulation results from average (red-dashed) and switch (green-
solid) mode. Top: duty ratios, middle: inductor current, bottom: output voltage.

57
3. MODELING OF THE ZVS-FB-PWM DC-DC
CONVERTER

The new procedure for the derivation of autonomous average circuit models given
in the previous chapter is complemented here and then applied to the ZVS-FB-PWM
converter to get a new model. Previous averaged models were based on steady-state
operation and neglected variables’ ripple effects. As a result their range of validity, i.e.
frequency, large signal excursions, was limited and could not make a smooth transition
between CCM and DCM operation. Comparison of simulation results between new and
previous model shows that most of those limitations have been overcome. Furthermore a
small-signal model is derived through linearization of the new average model and within
the circuit simulator; whereas previous small signal models were obtained through
graphical approximations of perturbations evolution.

3.1 ZVS-FB-PWM Converter Operation

The ZVS-FB PWM dc-dc converter and its typical switch structures (circuit
topologies) in CCM operation are shown in Fig. 3.1(a) and (b) whereas its typical
waveforms are depicted in Fig. 3.2. It operates with zero-voltage switching in both legs
and it is widely used in high power applications. Its complete analysis and design
considerations as well as its small signal models can be found in [S1] whereas some large
and small-signal models are provided in [T4, V5].

3.1.1. CCM operation

Figure 3.1(b) and 3.2 describe CCM operation of the converter through equivalent
circuit structures for each major switch configuration interval, i.e. Charging, Transfer
and Circulating, whose characteristics are summarized below [S1, V5], and waveforms
for bridge voltage, Vab, blocking capacitor voltage, Vab, primary current, Ip, bus current,
Ibus, filter inductor current, If, rectifier’s output voltage, Vs, and output voltage, V0.
Blocking capacitor voltage is assumed negligible with respect to both input and reflected
output voltage as Fig. 3.2 suggests.

Charging Stage. Starts at t0 when input voltage Vin is applied between nodes a and
b, and ends at t1 when primary current equals reflected filter inductor current. On the
primary side, after neglecting transformer’s magnetizing current and second and higher
order terms in Taylor’s series expansion, input voltage determines the rate of change of
current in the leakage inductor LLk, i.e. m1 in Fig. 3.2 and given by

Vin
m1 = , (3.1)
Llk

58
while rectifier diodes short circuit transformer’s secondary winding and hence the output
voltage V0, whose changes over a switching cycle are assumed negligible, determines the
rate of change of current in the filter inductor Lf, i.e. m4 in Fig. 3.2 and given by

V0
m4 = . (3.2)
Lf

According to (3.1) the change in primary current during this stage is

approximately given by

V 
I 1p − I 0p =  in  ⋅ (t1 − t0 ) = (m1) ⋅ (Dch ⋅ Ts ) , (3.3)
 Llk 

from where duty ratio for this stage, Dch, is given by

I 1p − I 0p
= Dch . (3.4)
m1 ⋅ Ts

Similarly from (3.2) the change in the filter inductor current during this stage is
approximately given by

V 
I 1f − I 0f =  0  ⋅ (t1 − t0 ) = (m4 ) ⋅ (Dch ⋅ Ts ) . (3.7)
L 
 f 

Current changes in (3.3) and (3.7) are related by the transformer’s turns ratio N, i.e.

(
I1f − I 0f = N ⋅ I1p − I 0p . ) (3.5)

Transfer Stage. Starts at t1 after primary current equals reflected filter inductor
current with transformer in normal operation and hence instantaneous primary current
and filter inductor current are related by the transformer’s turns ratio and ends at t2 when
Vab becomes zero. Reflection of input voltage and transformer’s leakage inductance to the
secondary side gives, for this stage, the equivalent circuit shown in Fig. 3.1. From here
the rate of change of primary current, m2 in Fig. 3.2, is given by

Vin − N ⋅ V0
= m2 , (3.6)
Llk + N 2 ⋅ L f

and from Fig. 3.2 the duty ratio for this stage is

I 1p − I 0p
Dtrf = Don − . (3.7)
m1 ⋅ Ts

59
 2
Llk /N Lf Charging
Vin /N
I bus /N If
Ibus Vs V0 RL
S1 S3 Lf
+ 2
+ Llk /N Lf
Vs If Cf RL Vo Transfer
Cb Llk - _
Vin+ Vin /N
I bus /N If
+ - N:1 Vs V0 RL
- a b
Vcb Ip

60
2
I bus /N Llk /N Lf
Circulating
S2 S4
Vin /N If
Vs V0 RL

a) Circuit schematic b) Switch structures in CCM

Fig. 3.1. ZVS-FB PWM converter

 S1 , S4 S2 , S4 S 2 , S3

Circulating
Charging

Transfer

Charging
V
V in
ab
Don⋅Ts

Dtrf ⋅Ts
VCb

m2 m3
Ip I bus
p I 2p I p
m1 I 1 3

I 0p
f I 2f
If I 0 N ⋅ m2 N ⋅ m3
If
m4
I 1f I 3f

Vs Vo

t0 t1 t2 t3 t

to to +Ts

Fig. 3.2. Typical ZVS-FB PWM converter waveforms in CCM.

61
 Change in filter inductor current is given by

 V / N −V 
I 2f − I 1f =  in 2 0  ⋅ (t2 − t1 ) = ( N ⋅ m2 ) ⋅ (Dtrf ⋅ Ts ), (3.8)
L / N +L 
 lk f 

t 2 − t1
where m2 is defined by the first bracket and Dtrf = .
Ts

Circulating stage starts when bridge voltage Vab becomes zero, primary current
and filter inductor current are related by the transformer’s turns ration, and the change in
inductor current for this interval is expressed as

 V0 
I 3f − I 2f =   ⋅ (t3 − t2 ) = ( N ⋅ m3 ) ⋅ [(1 − Don ) ⋅ Ts ] , (3.9)
 L / N2 + L 
 lk f 

where m3 is defined by the first bracket, and the commanded duty-ratio, Don, is given by

Don = Dch + Dtrf . (3.10)

Equations (3.1) through (3.6) together with Fig. 3.3 can now be used to calculate
the one-cycle average of filter inductor current If, i.e.

If =
(I 0
f
)
+ I 1f (I f + I 2f
⋅ (Don − Dtrf ) + 1
) (
I f + I 2f
⋅ Dtrf + 1
)
⋅ (1 − Don ) . (3.11)
2 2 2

The set (3.1) through (3.11) represents the algebraic constraint set needed to develop the
average circuit model.

3.1.2. DCM operation

Typical waveforms for DCM operation are shown in Fig. 3.4. Clearly there is no
charging stage and hence commanded duty cycle determines duration of transfer stage.

Peak filter inductor current is given by

 V / N −V 
I fpk =  in 2 0  ⋅ (t1 − t0 ) = ( N ⋅ m2 ) ⋅ (Don ⋅ Ts ) (3.12)
L /N +L 
 lk f 
and by

 V0 
I fpk =   ⋅ (t2 − t1 ) = ( N ⋅ m3) ⋅ (D 2 ⋅ Ts ) . (3.13)
 L / N2 + L 
 lk f 

62
 One-cycle average inductor current is calculated from (3.8) and (3.9) as

I fpk ⋅ (Don + D 2 )
If = , (3.14)
2

which gives the same DCM-CCM boundary condition as in the buck converter, i.e.

I fpk
If = . (3.15)
2

Equating (3.12) and (3.13) gives

Don ⋅ m2
D2 = (3.16)
m3

and its substitution together with (3.12) into (3.14) gives the algebraic constraint on one-
cycle average inductor current, i.e.

m2 ⋅ (Don ) ⋅ Ts 
2
m2 
If = 1 + . (3.17)
2  m3 

The same as in the buck converter, this constraint indicates that one-cycle average
filter inductor current is not an independent state.

3.2. New Average Circuit Model for the ZVS-FB Converter

Systematic application of the new procedure leads to the input-output structure

average model of the ZVS-FB PWM dc-dc converter shown in Fig. 3.4(a) as detailed
next.

3.2.1. Step 1: Fast/slow classification of state variables

From Figs. 3.1 and 3.2, filter inductor current and output capacitor voltage qualify
as slow variables in CCM to be used as states in the average circuit model. However in
DCM only the output capacitor remains as a slow state. Filter inductor current stays at
zero during a significant amount of time within a switching cycle, which leads to having
its one-cycle average fully determined by present switching cycle condition and hence
being converted to a fast variable.

Primary current is not considered a relevant average state variable, even though it
corresponds to leakage inductor state variable, because its moving average is zero in
steady state operation and exhibits large components at one half the switching frequency
and higher harmonics during transient regime. In other words no new information would

63
be provided in steady state and time varying effects would have to be included in the
model.

3.2.2. Step 2: LTI input/output parts

Output filter and input voltage source get selected as LTI networks according to
circuit topologies in Fig. 3.1(b).

3.2.3. Step 3: “Independent” variable drawn from LTI input network and
“dependent” variable delivered to LTI output network

Average bus current is the “dependent variable” drawn from input voltage source
whereas secondary rectifier’s output voltage is the “independent variable” applied to the
output filter during CCM operation. On the other hand one cycle average inductor current
becomes the sought independent variable fed to the output section during DCM operation
the same as in the buck converter.

3.2.4. Step 4: Calculation of one-cycle average for the variables in the previous step

CCM. According to Figs. 3.1(b), 3.2 and 3.4(c) rectifier voltage is equal to zero during
charging stage; it becomes a function of input source voltage and output capacitor
voltage, during transfer stage after neglecting blocking capacitor voltage, i.e.

Vin L
⋅ L f + V0 ⋅ lk2
Vs = N N , t1 ≤ t ≤ t2 , (3.18)
Llk
+ Lf
N2

and only a function of capacitor voltage during circulating stage given by

Llk
V0 ⋅
Vs = N2 , t 2 ≤ t ≤ t1 . (3.19)
Llk
+ Lf
N2

From (3.18), (319) and Fig. 3.2 the one-cycle average rectifier voltage given to controlled
source V2 can be expressed as

Vin L L
⋅ L f + V0 ⋅ lk2 V0 ⋅ lk2
V2 = Vs = N N ⋅D + N ⋅ (1 − D ) . (3.20)
Llk trf
Llk on
+ L f + L f
N2 N2

64
 S1 , S4 S2 , S4 S 2 , S3

Circulating
Transfer

Transfer
Idling
Vab V in
Don⋅Ts
D2⋅Ts
VCb

I ppk
Ip m1 m2 I bus

I
f I fpk
N ⋅ m1 N ⋅ m2
If

V V0
s

t0 t1 t2 t3 t
to to +Ts

Fig. 3.3. Typical ZVS-FB PWM converter waveforms in DCM.

65
 The average circuit model shown in Fig. 3.4(b) includes transformer’s leakage
inductance reflected to the secondary side to highlight its dynamic effects, which are
implicitly included in (3.20). The model becomes equivalent to that in Fig. 3.4(a) if Veq is
computed to make V2 appear in between the two inductors, that is, to have the same
average voltage delivered to the output filter. Therefore Veq is given by

Llk
V0 ⋅
Vin N 2 ⋅ (1 − D ) .
Veq = ⋅ Dtrf + ch (3.21)
N Lf

Fig. 3.4 indicates that controlled current source I1 corresponds to one cycle
average bus current. From Figs. 3.1(b) and 3.2, I1 can be computed as

I 1 = I bus =
(− I 0
p
+ I 1p )
⋅ Dch + 1
(
I p + I 2p )
⋅ Dtrf . (3.22)
2 2

Calculation of Dtrf is again carried out on line in the simulator by closing the loop
around operational amplifiers to find the root located between 0 and Don. Equations (3.1)
through (3.22) can be combined to find the expression with Dtrf as the only unknown or
they can be arranged to solve for as many of the unknown quantities as desired.

DCM. One-cycle average filter inductor current is now given by (3.14) and the
average circuit model is shown in Fig. 3.5(a). Since this situation its very similar to that
found in the buck converter model the value I f may be enforced by adjusting, in the
average circuit model shown in Fig. 3.4, controlled source V2, which in turn depends on
D2. Therefore filter inductor current can be treated the same as in the buck converter
model, i.e. a loop around an operation amplifier that enforces algebraic constraint (3.14).

Bus current, according to (3.12) and Figs. 3.2 and 3.4 is given by

I fpk ⋅ Don m2 ⋅ (Don ) ⋅ Ts

2
I1 = = . (3.23)
2 2

3.2.5. Step 5: Calculation of algebraic constraints

These constraints are already described in (3.1) through (3.23) both for CCM and
DCM operation.

3.2.6. Step 7: Implementation of circuit oriented simulation

Fig. 3.6 shows the same technique used in Chapter 2 to compute, in real time
during the simulation, Dtrf and D2 both in CCM and DCM for the average model.

66
3.3. Previous Average Models for the ZVS-FB Converter

Models presented in [T4, V5] used the PWM switching model in [V8]. However
[T4, V5] neglects some effects of transformer’s leakage inductance upon rectifier’s
output voltage and upon filter inductor current slopes. As a result this average model
neither makes a smooth transition between CCM and DCM nor gives an accurate small-
signal model through linearization.

[V5] does not provide a large signal average model but only a DC (steady-state)
model and a small-signal model is developed by adding some controlled sources to the
small-signal model, derived through the PWM switching model in [V8], for the Buck
converter. It also neglects some effects of transformer’s leakage inductance upon
rectifier’s output voltage and upon filter inductor current slopes.

None of these models follows the correct introduction order for perturbation and
steady-state constraints pointed out in [V3] and hence validity-range of derived small-
signal models gets compromised.

3.4. Simulation Results

New and previous [T4] average models of the ZVS-FB PWM dc-dc converter get
compared to its switching model through transient simulations. These simulations are
carried out for several sets of parameter values similar to those used in [V5], which are
listed in Table 1. Commanded duty-ratio Don for all simulation is shown on top graph of
Fig. 3.23. Appendix B contains templates for the Saber simulator.

State variables from the new average model very closely follow moving average
of their respective counterparts in the switching model for all parameter sets, Figs. 3.7
through 3.20, whereas state variables from previous model can only exhibit good tracking
under special conditions, Figs. 3.14, 3.17 and 3.19, and can present faster or slower
dynamics than that of the switching model depending of operating conditions, Figs. 3.9,
3.11, 3.14 and 3.190. Furthermore the new average model maintains excellent tracking
during transient regimes that go back and forth between CCM and DCM as Figs. 3.8, 3.9,
3.10, 3.13, 3.16, 3.17 and 3.18 show.

3.4.1. Transient simulations for parameter set 1

Simulations results for this set are shown in Fig. 3.8 through 3.10. Even though
the ratio of filter inductance to transformer’s leakage inductance is 60 and hence effects
of the latter upon average behavior might be assumed negligible, as the previous model
[T4] does, Figs. 3.8 through 3.10 indicate that those effects are still relevant. The new
model maintains excellent state variables tracking for back and forth transitions between
CCM and DCM operating modes whereas the previous model [T4] lacks it due to the
loose approximation to model leakage inductor influence as Fig. 3.7, 3.9 and 3.10 clearly
show. The large in-rush current shown in Figs. 3.7 and 3.8, not allowed in practice by the

67
start-up sequence, was used here to solely illustrate average circuit model tracking
properties. Commanded duty-ratio Don for all simulation is shown on top graph of
Fig. 3.19. Figs. 3.7 and 3.8 show responses to zero initial conditions for all models.

Table 1 Parameter value sets for transient

response of ZVS-FB converter.

Parameter Set 1 Set 2 Set 3 Set 4 Set 5

Turns Ratio 5 1 1 5 1

Leakage Induc. [µH ] 5 30 5 5 30

Filter Induc. [µH ] 12 30 12 12 100

Filter Cap. [µF ] 100 100 100 200 100

Load Resist. [Ω ] 20 75 5 10 75

Lf/(Llk/N2) 60 1 2.4 60 3.33

Vin [V ] 600 600 600 600 600

3.4.2. Transient simulations for parameter set 2

Simulation results for this set are shown in Fig. 3.11 through 3.13. The ratio of
filter inductance to transformer’s leakage inductance is 1 and hence effects of the latter
upon average behavior are very strong, contrary to what the previous model assumes.
Fig. 3.12 clearly shows three different slopes on inductor current waveforms, as
considered by the new model derivation above, and very close tracking characteristics of
the new model for transitions between CCM and DCM operating modes. In contrast to
this the previous model completely lacks tracking. Furthermore the previous model
exhibits slower dynamics than the correct one for certain operating conditions during the
transient and faster dynamics than the correct one for other operating conditions. As a
result the previous model cannot be used either for transient or stability analysis.

68
3.4.3. Transient simulations for parameter set 3

Figures 3.14 through 3.16 show simulation results for this special set of parameter
values. The latter were selected so that the steady state part of the simulation from the
previous average model matched very well results from the other two models but the fast
transients show not so good an agreement. Since results from previous average model for
set 2 showed faster and slower than correct dynamics it seemed possible to get a correct
response for certain range of parameter values and operating conditions. Obviously this
example warns about apparent good results when the ratio filter inductance to reflected
leakage inductance is relatively low. The same excellent tracking is observed for the new
model.

3.4.4. Transient simulations for parameter set 4

Figures 3.20 and 3.21 show simulation results for another special set of parameter
values. The latter were selected very similar to set 1, i.e. large ratio of filter inductance to
reflected leakage inductance, but to provide smooth transition between CCM and DCM
for the previous average model and to coincide with the other two models. These results
highlight the region of validity for the previous model. Once again the new model shows
excellent tracking.

Table 2. Parameter value set I for small-signal model and transient

response of Buck, ZVS-FB and ZVZCS-FB converters.

Parameter Buck ZVS ZVZCS

Turns Ratio NA 6 6

Leakage Induct. [µH ] NA 1 1

Blocking Cap. [µF ] NA 20 1

Filter Induc. [µH ] 2 2 2

Filter Cap. [µF ] 200 200 20

Load Resist. Ω 1.1 1.1 1.1

Saturable Reactor [µV − sec] NA NA 60

Vin [V ] 55 330 330

69
 Table 3. Parameter value set II for small-signal model and transient
response of Buck, ZVS-FB and ZVZCS-FB converters.

Parameter Buck ZVS ZVZCS

Turns Ratio NA 1 1

Leakage Induct. [µH ] NA 1 1

Blocking Cap. [µF ] NA 20 1

Filter Induc. [µH ] 20 20 20

Filter Cap. [µF ] 50 50 50

Load Resist. Ω 2.2 2.2 2.2

Saturable Reactor [µV − sec] NA NA 60

Vin [V ] 330 330 330

3.4.5. Transient simulations for parameter set 5

Figures 3.22 and 3.23 show simulation results for another special set of parameter
values. Now the latter were selected very similar to set 2, i.e. low ratio of filter
inductance to leakage inductance. However the results look quite different from those for
set 2 since good tracking is seem from the previous average model. Here the new average
model also exhibited excellent tracking.

3.4.6 Transient and small-signal simulation results.

Results from transient and linearization, within the same circuit simulator, for the
average model with two different resistive load values are shown in Figs. 3.21 through
3.24 for Buck, ZVS and ZVZCS converters. The latter, thoroughly analyzed in chapter 4,
is included here to highlight the contrast between the two soft-switched converters with
respect to the damping added to the output filter. The transfer functions shown in Figs.
3.22 and 3.24, are Don to filter inductor current and Don to capacitor voltage. In the buck

70
converter these transfer functions have the same shape, i.e. pole frequency and damping,
as those from output low pass filter except for a different gain factor. Both ZVS-FB and
ZVZCS-FB converters alter output filter damping coefficient and pole frequency. These
changes depend on parameters values and/or operating conditions for both ZVS-FB and
ZVZCS-FB converters. With parameter value Set I in Table 2 both soft-switched
converters change the damping factor by a fairly large amount albeit in opposite
directions. For the other parameter value set the ZVZCS-FB converter exerts a very small
reduction in damping whereas the ZVS-FB converter introduces a large increment.

71
 Lf
I bus
I1
If
Vin + I1 V2 RL
- Vo

If
a) Input-output structure model
Vs V2

Lf

72
Llk /N2
to to +Ts t
If
Vin + I1 Veq V2 RL
- Vo
I 1 = I bus (t ) V2 = Vs (t )

b) Mixed input-output-internal structure c) Waveforms for controlled-source average

model calculation

Fig.3.4. ZVS converter equivalent average models and waveforms in CCM.

 I1
I bus

If I2
Vin + I I1 I2
+ RL
- Vo
Vs vo

73
to to +Ts t

I 1 = I bus (t ) I 2 = I f (t )

c) Waveforms for controlled-source average

a) Input-output structure model
calculation

Fig.3.5. ZVS converter equivalent average model and waveforms in DCM.

 Limiter

Out
D2
1 − Dtrf

In

m2
Eqn (3.4)
m3 C
D  Eqn (3.16)
 On 
I  zero R
 f 
Z=   D2 ⋅ m2 ⋅ Ts − i pk
=0 _
V  f OP
 in  +
V 
 o 
...

Don − Dch − Dtrf = 0 zero R

_
OP
+

Dtrf Out

Don

In

Limiter

Fig. 3.6. Analog schematic for computation of Dtrf and D2.

74
 Proposed Previous
Model Model

Previous
Model

Switching and Proposed

Model (Overlapped)

Lf
= 60
N 2 ⋅ Llk

Fig. 3.7. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average(black) models for parameter set 1
with zero initial state for all models.

75
 Previous
Model

Proposed
Model

Previous
Proposed Model
Model

Switching Model

Lf
= 60
N 2 ⋅ Llk

Fig. 3.8. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 1
with zero initial state for all models.

76
 Proposed Previous
Model Model

Previous
Model

Switching and Proposed

Model (Overlapped)
Lf
= 60
N ⋅ Llk
2

Fig. 3.9. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 1
with zero initial state for all models.

77
 Previous
Model

Proposed
Model

Previous
Model

Switching and Proposed

Model (Overlapped)
Lf
= 60
N ⋅ Llk
2

Fig. 3.10. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 1
with zero initial state for all models.

78
 Previous
Model

Proposed
Model

Previous
Model

Switching and Proposed

Model (Overlapped)

Lf
=1
N 2 ⋅ Llk

Fig. 3.11. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 2
with zero initial state for all models.

79
 Previous
Model
Proposed
Model Switching
Model

Previous
Model

Proposed
Model

Lf
Switching =1
N 2 ⋅ Llk
Model

Fig. 3.12. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 2
with zero initial state for all models.

80
 Previous
Model

Proposed
Model

Previous Lf
=1
Model N 2 ⋅ Llk

Switching and Proposed

Model (Overlapped)

Fig. 3.13. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 2
with zero initial state for all models.

81
 Proposed
Model

Previous
Model

Switching and Proposed

Model (Overlapped)

Previous
Model

Lf
= 2.4
N 2 ⋅ Llk

Fig. 3.14. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 3
with zero initial state for all models.

82
 Proposed
Model

Previous
Model
Switching
Model

Lf
Proposed = 2.4
Model N 2 ⋅ Llk

Previous
Model
Previous
Model

Fig. 3.15. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 3
with zero initial state for all models.

83
 Previous
Model

Proposed
Model

Lf
= 2.4
N 2 ⋅ Llk

Proposed
Model

Switching and Proposed

Model (Overlapped)

Fig. 3.16. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 3
with zero initial state for all models.

84
 Previous and Proposed
Model (Overlapped)

Previous, Proposed and

Switching Model
(Overlapped)

Lf
= 60
N 2 ⋅ Llk

Fig. 3. 17. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 4
with zero initial state for all models.

85
 Previous and Proposed
Model (Overlapped)

Previous, Proposed and

Switching Model
(Overlapped)

Lf
= 60
N 2 ⋅ Llk

Fig. 3.18. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 4
with zero initial state for all models.

86
 Commanded Duty
Cyacle)

Proposed
Model Dtrf Proposed
Model D2

Proposed
Model

Previous
Model
Switching and Proposed
Model (Overlapped)

Previous
Model

Lf
= 3.3
N 2 ⋅ Llk

Fig. 3.19. Duty ratios (top), filter inductor current (middle) and capacitor voltage
(bottom) from switching (green), new average (pink) and previous average (black)
models for parameter set 5 with zero initial state for all models.

87
 Commanded Duty
Cyacle)

Proposed
Model Dtrf

Previous
Model

Proposed
Model

Switching and Proposed Lf

= 3.3
Model (Overlapped) N ⋅ Llk
2

Previous
Model

Fig. 3.20. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), new average (pink) and previous average (black) models for parameter set 5
with zero initial state for all models.

88
 Buck
ZVS-FB

ZVZCS-FB

ZVZCS-FB

Buck

ZVS-FB

Fig. 3.21. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVS-FB (blue) and ZVZCS-FB
(black) converters with parameter set I.

89
 ZVZCS-FB Buck

ZVS-FB

Buck

ZVS-FB

ZVZCS-FB

ZVZCS-FB Buck

ZVS-FB

Buck

ZVS-FB

ZVZCS-FB

Fig. 3.22. Capacitor voltage (top) and filter inductor current (bottom) transfer
functions from new average models for Buck (red), ZVS-FB (blue) and ZVZCS-FB
(black) converters with parameter set I.

90
 Buck

ZVZCS-FB

ZVS-FB

Buck

ZVZCS-FB

ZVS-FB

Fig. 3.23. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVS-FB (blue) and ZVZCS-FB
(black) converters with parameter set II.

91
 ZVZCS-FB
Buck

ZVS-FB

Buck

ZVS-FB

ZVZCS-FB

ZVZCS-FB Buck

ZVS-FB

Buck

ZVS-FB

ZVZCS-FB

Fig. 3.24. Capacitor voltage (top) and filter inductor current (bottom) transfer
functions from new average models for Buck (red), ZVS-FB (blue) and ZVZCS-FB
(black) converters with parameter set II.

92
4. MODELING OF THE SATURABLE INDUCTOR
BASED ZVZCS-FB-PWM DC-DC CONVERTER

The new procedure for the derivation of autonomous average circuit models given
in Chapter 2 is again complemented here and then applied to the ZVZCS-FB-PWM
converter to get its circuit average model, which is a new result.

Comparison of simulation results between average and switching model shows

that most of the average dynamics is preserved. Furthermore a small-signal model is
derived through linearization of the new average model within the circuit simulator and
compared to those for buck and ZVS models.

4.1 ZVZCS-FB-PWM Converter Operation

The ZVZCS-FB topology introduced in [C11], Fig. 4.1(a), and whose switch
structures and typical waveforms for CCM operation are shown in Fig. 4.1(b) and 4.2,
respectively, operates with zero-voltage switching in the leading leg and zero-current
switching in the lagging leg for very wide load and line ranges. Although initially
intended to have its lagging leg built with IGBTs, the latter’s switching speed limitations
prevent their application at very high frequencies, where MOSFETs become the only
choice. However, by having conduction losses in the primary side strongly reduced
through almost complete elimination of freewheeling stage in that side, the ZVZCS
topology can still provide high efficiency for wide line range even with MOSFETs.

Appendix C provides detailed design procedure for the converter as well as its
waveforms and their exact describing equations for CCM operation. In this chapter only
brief descriptions of waveforms relevant to the development of the averaged circuit
model and their simplified expressions are presented.

4.1.1. CCM operation

Fig. 4.1(b) shows major topological stages for CCM operation of the ZVZCS
converter, i.e. Blocking, Charging, Transfer, Resetting and Off, whose characteristics are
summarized below [C11]. Fig. 4.2 shows typical waveforms for bridge voltage, Vab,
primary current, Ip, bus current, Ibus, blocking capacitor voltage, Vcb, filter inductor
current, If, rectifier’s output voltage, Vs and output voltage, V0.

Assume the switching cycle starts with the blocking stage at to, when bridge
voltage Vab becomes positive and saturable reactor blocks any primary current, and ends
at t1 when the reactor gets saturated. The sum of input voltage and blocking capacitor
voltage determines the rate of change of flux in the saturable reactor. The change of flux
during this stage amounts to

93
 2
Llk /N Lf
VSA Blocking
Vin + Vcb
N I
Ibus /N If
Vs V0 RL

2
Llk /N Lf Charging
Vin +Vcb
N Ibus /N If V0
S1 S3 Vs RL
Lf
2
Llk /N Lf
+ + Vin + Vcb Transfer
Vs If Vo N Ibus /N If
L s Cb Llk
- - Vs V0 RL
+
Vin 2
N:1 Llk /N Lf
+ - Resetting

94
- a b Vin + Vcb
Vcb Ip N Ibus /N If
Vs V0 RL

2
VSA Llk /N Lf
Off
S2 S4 Vin +Vcb
N Ibus /N If
Vs V0 RL

a) Circuit schematic b) Switch structures in CCM

Fig.4.1. ZVZCS converter

  Vin + Vcpk   V + Vcpk 
∆φ blk = (t1 − t0 ) ⋅   = (Dblk ⋅ Ts ) ⋅  in  , (4.1)
 N sr   N sr 

where Dblk, Nsr and Vcpk are blocking stage duty-ratio, saturable reactor number of turns
and peak blocking capacitor voltage, respectively. On the secondary side output voltage
determines rate of change in filter inductor current, m4 in Fig. 4.2, as

V0
m4 = . (4.2)
Lf

During charging stage, (t1,t2), the same rate of change applies to filter inductor
current whereas the change in primary current, after neglecting transformer’s
magnetizing current and second order terms in Taylor’s series expansion, is
approximately given by

V +V 
I 2p =  in cpk (t2 − t1 )⋅ = (m1) ⋅ (Dch ⋅ Ts ) , (4.2)
 LLk 

where slope m1, shown in Fig. 4.3, is defined by the first bracket, Dch corresponds to
charging stage duty ratio and the remaining quantities are defined in Fig. 4.2.

At time instant t2 primary current and filter inductor current are related by
transformer’s turns ratio, i.e.

I 2f = I 2p ⋅ N , (4.3)

and they remain so through transfer stage, which ends at t3 with commanded duty-cycle
Don.

Don ⋅ Ts = (t3 − t0 ) = (Dblk + Dch + Dtrf )⋅ TS . (4.4)

Reflection of input voltage and transformer leakage inductance to the secondary

side leads to the equivalent circuit for this stage, Fig. 4.1(b). Change in the filter inductor
current, after neglecting blocking capacitor effects, is approximately given by

 Vin 
 −V 
 ⋅ (t3 − t2 )⋅ = ( N ⋅ m2 ) ⋅ (Dtrf ⋅ Ts ) ,
I −I =
f f N O (4.5)
3 2
 Llk 2 + L f 
 N 

where slope N ⋅ m2 is defined by the first bracket and the other terms by Fig. 4.2.
Blocking capacitor voltage, Vcb, is neglected here to simplify the derivation and because
its contribution is very small as later simulation results confirm.

95
 S1 , S4 S2 , S4 S 2 , S3

Charging

Resetting
Blocking

Transfer

Off
Vab V in
D on ⋅ T s D on ⋅ T s

Vcb Vcpk

m2
Ip I bus
m1 p I 3p m3
I 2

I 3f
N ⋅ m2
I m4
f
m4
I 2f If I 4f

Vs
Vo

t0 t1 t2 t3 t4 t5 t

to t o + Ts

Figure 4.2. ZVZCS-FB PWM primary and filter inductor current waveforms in CCM.

96
 Resetting stage starts at t3 when bridge voltage Vab becomes zero and it ends when
primary current does the same at t4. Duration of this stage is given by

1  Ip Llk 
t4 − t3 = Dres ⋅ TS = ⋅ arcsin 3 ⋅ . (4.6)
Llk ⋅ Cblk V 
 cpk Cblk 

Off stage begins at t4 when saturable reactor blocks any primary current by taking
Vcpk as its flux rate of change and it ends at (to+Ts) with half of primary switching cycle
when Vab becomes negative as shown in Fig. 4.2. During this stage the change in flux
across the saturable reactor is given by

Vcpk ⋅ (1 − Don − Dres ) ⋅ Ts

∆φoff = , (4.7)
N sr

which together with saturable reactor volt-second blocking capability determines

blocking stage duration, i.e.

∆φ Blk = 2 ⋅ φ sat − ∆φOff , (4.8)

where ∆φblk is given by (4.1) and 2 ⋅ φsat is the volt-second blocking capability of the
saturable reactor.

Expressions for peak blocking capacitor voltage, Vcpk , filter inductor current
average and ripple values, I L ≡ I f and ∆I f are calculated next to complete the set of
equations. An approximation to Vcpk value is obtained by looking at converter’s steady-
state operation and by taking into consideration the relevance of each stage’s duration
upon change in the capacitor voltage. These voltage changes during transfer and resetting
stages are respectively approximated by

I L ⋅ Dtrf ⋅ Ts
∆Vc−trf = (4.9)
N ⋅ Cb
and

∆Vc − res =
(I )⋅ D
3
f
⋅ Ts
res
. (4.10)
2 ⋅ N ⋅ Cb

From Figs. 4.2 and 4.5, after neglecting voltage change during charging stage,
Vcpk is given by

97
 S1 , S4 S2 , S4 S 2 , S3

Resetting
Blocking

Transfer

Idling
Off
Vab V in
D on ⋅ T s D2 ⋅ T s
D on ⋅ T s

Vcb Vcpk

I ppk
Ip m2 m3 I bus

I I fpk
f N ⋅ m2 m4
If

Vs Vo

t0 t1 t2 t3 t4 t5 t
to t o + Ts

Figure 4.3. ZVZCS-FB PWM primary and filter inductor current waveforms in DCM.

98
 ∆Vc−trf + ∆Vc−res
Vcpk = . (4.11)
2

On the other hand ∆I f is calculated as

∆I f = Dtrf ⋅ (I 3f − I 2f ) + (1 − Dtrf )⋅ (I 4f − I 3f ) , (4.12)

where

V 
I 4f − I 3f =  O  ⋅ (1 − Dtrf )⋅ Ts = m4 ⋅ (1 − Dtrf )⋅ Ts . (4.13)
L 
 f 

4.1.2. DCM operation

Typical waveforms for DCM operation are shown in Fig. 4.3. Clearly there is no
charging stage and hence commanded duty cycle equals the sum of blocking and transfer
stages, i.e.

Don = Dblk + Dtrf . (4.14)

Peak filter inductor current is given by

 V / N −V 
I fpk =  in 2 0  ⋅ (t2 − t1 ) = ( N ⋅ m2 ) ⋅ (Dtrf ⋅ Ts ) (4.15)
L /N +L 
 lk f 

and by

 V0 
I fpk =   ⋅ (t3 − t2 ) = (m4 ) ⋅ (D 2 ⋅ Ts ) . (4.16)
 L / N2 + L 
 lk f 

One cycle average inductor current is calculated from (4.15) and (4.16) as

I fpk ⋅ (Dtrf + D 2 )
IL = I f = , (4.17)
2

which gives the same DCM-CCM boundary condition as in the buck converter, i.e.

I fpk
If = . (4.18)
2

99
Equating (4.15) and (4.16) gives

Dtrf ⋅ N ⋅ m2
D2 = (4.19)
m4

and its substitution into (4.17) gives the algebraic constraint on one-cycle average
inductor current, i.e.

N ⋅ m2 ⋅ (Dtrf ) ⋅ Ts 
2
N ⋅ m2 
If = 1 + . (4.20)
2  m4 

As in the Buck converter, this constraint indicates that one-cycle average filter
inductor current is not an independent average state.

Equation (4.1) still applies during blocking stage and (4.7) now represents the
change in flux across the saturable reactor during the sum of intervals for off and idling
stages. On the other hand expressions for capacitor voltage, i.e. (4.9), (4.10) become

I fpk ⋅ Dtrf ⋅ Ts
∆Vc −trf = , (4.21)
2 ⋅ N ⋅ Cb

and

I fpk ⋅ Dres ⋅ Ts
∆Vc −res = , (4.22)
2 ⋅ N ⋅ Ccb

whereas (4.11) remains the same.

4.2. New Average Circuit Model for the ZVZCS-FB Converter

Systematic application of the new procedure leads to the input-output structure

average model of the ZVZCS-FB PWM dc-dc converter shown in Fig. 4.4(a) as detailed
next.

4.2.1. Step 1: Fast/slow classification of state variables

Figure 4.2 indicates that filter inductor current and output capacitor voltage qualify as
slow variables in CCM to be used as states in the average circuit model. However in
DCM only the output capacitor remains as a slow state. Similarly to the situation in
Chapter 3 filter inductor current stays at zero during a significant amount of time within a
switching cycle, which leads to having its one-cycle average fully determined by present
switching cycle condition and hence being converted to a fast variable.

100
 Lf
Vab Vin
IL
Vin + I1 V2 RL
- Vo

Ibus
I1

a) Input –output structure

If

101
Llk /N2 Lf V2
Vs
IL to to +Ts t
Vin + I 1 Veq V2 I RL
- Vo
I1 = Ibus (t ) V2 =Vs (t )

b) Mixed input-output-internal structure c) Typical waveforms

Fig.4.4. ZVZCS converter equivalent average models and waveforms in CCM.

 Again primary current is discarded as a relevant average state variable, even
though it corresponds to leakage inductor state variable, because its moving average is
zero in steady state operation and exhibits large components at one half the switching
frequency and higher harmonics during transient regime. In other words no new
information would be provided in steady state and time varying effects would have to be
included in the model.

Blocking capacitor voltage gets classified as a fast variable and its waveform in
Fig. 4.2 indicates that it is an energy holding element. Its treatment is presented later in
this chapter.

4.2.2. Step 2: LTI input/output parts

Output filter and input voltage source get selected as LTI networks according to
circuit topologies in Fig. 4.1(b).

4.2.3. Step 3: “Independent” variable drawn from LTI input network and
“Dependent” variable delivered to LTI output network

From Fig. 4.1(b) it looks apparent that average bus current is the “Dependent
variable” drawn from input voltage source whereas secondary rectifier’s output voltage
is the “Independent variable” applied to the output filter during CCM operation. On the
other hand from Fig. 4.3 it is clear that one cycle-average inductor current becomes the
sought Independent variable fed to the output section during DCM operation the same as
in the ZVS-FB converter.

4.2.4. Step 4: Calculation of one-cycle average for the variables in the previous step

CCM. According to Figs. 4.1(b), 4.2 and 4.4(c) rectifier’s voltage is a function of
input, blocking capacitor and output voltages during transfer stage, i.e.

Vin + Vcb L
⋅ L f + V0 ⋅ lk2
Vs = N N , (4.23)
Llk
+ Lf
N2

whereas the rest of the switching cycle it becomes zero. From (4.23) and Fig. 4.2 the one
cycle average rectifier voltage can be expressed as

(V
in + Vcb) L
⋅ L f + V0 ⋅ lk2
Vs = N N ⋅D (4.24)
Llk trf
+ L f
N2

102
 Vcpk
Vcb
mcb
A2
0
A1
A3

-Vcpk
Dtrf ⋅ Ts

IL A1 -- A2
mcb ≈ Vcb =
N ⋅ Cb Dtrf ⋅ Ts

Figure 4.5. Calculation of average blocking capacitor voltage.

103
where Vcb is the average of blocking capacitor voltage during transfer stage. According
to Fig. 4.5 Vcb is directly proportional to the difference between areas A2 and A1, i.e.

A2 − A1 ( A2 + A3 ) − ( A1 + A3 )
Vcb = = (4.25.a)
Dtrf ⋅ Ts Dtrf ⋅ Ts

 I Dtrf ⋅ T 
(V ⋅ Dtrf ⋅ Ts ) −  L ⋅ 
2 
cpk
 N ⋅ Cb I L ⋅ Dtrf ⋅ Ts
Vcb = = Vcpk − , (4.25.b)
Dtrf ⋅ Ts 2 ⋅ N ⋅ Cb

where the slope of blocking capacitor voltage during transfer stage is approximated by

IL
mcb ≈ . (4.26)
N ⋅ Cb

The average circuit model shown in Fig. 4.4(b) includes transformer’s leakage
inductance reflected to the secondary side to highlight its dynamic effects, implicitly
included in (4.25). As in the ZVS-FB converter case Veq can be computed to make V2
appear in between the two inductors, that is, to have the same average voltage delivered
to output filter. Therefore Veq is given by

Vin + Vcb V ⋅L
Veq = ⋅ Dtrf − 02 lk ⋅ (1 − Dtrf ). (4.27)
N N ⋅ Lf

Fig. 4.5 indicates that controlled current source I1 corresponds to one cycle
average bus current. From Figs. 4.2, and 4.4(c) I1 can be computed as

I 1 = I bus =
I P2 (I 2 + I P3
⋅ Dch + P
)⋅ Dtrf . (4.28)
2 2

DCM. One-cycle average filter inductor current is now given by (4.17). Since this
situation is the same as that found both in the buck and ZVS-FB converter models the
value I f must be enforced by adjusting, in the average circuit model, controlled source
V2, which in turn depends on D2. Therefore filter inductor current can be treated the same
as in the previous two converter models, i.e. a loop around an operation amplifier that
enforces algebraic constraint (4.17).

Calculation of Dtrf is again carried out on line in the simulator by closing the loop
around operational amplifiers to find the root located between 0 and Don. Equations (4.1)

104
through (4.29) can be combined to find an expression with Dtrf as the only unknown or
they can be arranged to solve for as many of unknown quantities as desired.

Bus current, according to (4.15) and Fig. 4.3 is given by

m2 ⋅ (DTrf )
2
I Fpk ⋅ DTrf ⋅ Ts
I1 = = . (4.29)
2⋅ N 2

4.2.5. Step 5: Calculation of algebraic constraints

These constraints are already described in (4.1) through (4.22) both for CCM and
DCM operation.

4.2.6. Step 7: Implementation of circuit oriented simulation

Fig. 4.6 shows the same technique used in the previous two chapters to compute,
in real time during the simulation, Dtrf and D2 both in CCM and DCM for the average
model.

4.2.7. Identification and modeling of energy holding elements in fast dynamic

subsystems

An energy holding element is a reactive component that does not appear as a

relevant state in the average model and its state variable (voltage for capacitors, current
for inductors):

a) gets classified as fast type.

b) has zero moving average in steady state operation and exhibits large
components at one half the switching frequency and higher harmonics
during transient regime.
c) exhibits relatively large peak-to-peak excursions.
d) exhibits nonzero and relatively large constant value during a significant
time interval within a switching cycle.
e) exerts a significant influence upon switching instants and/or
“Dependent/Independent” controlled sources’ one-cycle average value.

Since this state variable is the integral of a piece-wise continuous function it is

continuous and from (a) and (b) its temporary nonzero constant value depends on the
history of that integrand, in general a function of some state variables. Because of (d) this
“nonzero constant value” is a critical parameter in the converter constraint equations and
its dynamics must be appropriately modeled. Sample data models can very easily and
accurately describe these effects whereas high order average continuous models need be
used for the same accuracy.

105
 Limiter

Out
D2
1-DTrf

In

m1
Eqn (4.2)
m2 C
D  Eqn (4.5)
 On 
I
 f 
 zero R _
Z=   D2 ⋅ m2 ⋅ Ts − i Lpk = 0
V  OP
 in  +
V 
 C 
C
...

DOn − DBlk − DCh − DTrf = 0 zero R

_
OP
+

DTrf Out

In

Limiter

Figure 4.6. Analog computation of Dtrf and D2.

106
 Ts
R=
C
Limiter
C
Out
IL R D2
_ − I L− slow
OP 1-DTrf
+

In

∆Vc − trf
I L − slow ⋅ Dtrf ⋅ Ts /N ⋅ C b
∆Vc − Res
(I )⋅ D
C
res ⋅ Ts /2 ⋅ N ⋅ C b
f
D  3
 On 
I
 L 
 zero R _
Z=   D2 ⋅ m2 ⋅ Ts − i Lpk = 0
Vin  OP
+

V

 I 3f
 C 
I L− slow + ∆I L /2 C

DOn − DBlk − DCh − DTrf zero R

_
OP
+

DTrf Out

In

Limiter

Figure 4.7. Analog implementation of dynamic relationship between filter inductor

current an blocking-capacitor peak voltage .

107
 Here a heuristic approach is followed to obtain a simple and effective
representation of this energy holding element effects. Circuit simulations verify
usefulness of this representation.

In our ZVZCS-FB converter blocking capacitor reaches Vcpk at the end of

resetting stage and holds it constant until the end of blocking stage. Duration of the latter
is inversely related to Vcpk and hence to the long history of IL whereas that of charging
stage is directly related to IL in the present switching cycle. As a consequence, an
intricate relation among circuit parameters determines whether positive or negative
damping is added to the output filter as summarized next and explained in more detail in
Appendix C for steady-state operation.

The change in damping is directly related to the loss of duty-cycle,

Don − Dtrf = Dblk + Dch , (4.30)

and hence inversely related to the change in transfer stage duty ratio. Since duration of
the charging stage, i.e. Dch, is proportional to IL the change in duration of blocking stage
with respect to IL has to overcome that in Dch for damping of the output filter to get
reduced (intrinsic positive feedback). A low Cblk value in the ZVZCS converter, as
compared to that in the ZVS converter, leads to a large change in Vcpk with IL. This in turn
makes the product Vcpk ⋅ Doff ⋅ Ts bigger, which produces a reduction in blocking stage
duration, since saturable-reactor volt-second blocking capability is constant. The size of
that reduction will strongly depend on blocking capacitor value and saturable reactor
volt-second blocking capability. Furthermore, it is possible to have an increase in duty-
cycle loss for some component values, especially when they resemble those used in the
ZVS converter.

Moreover, the amount of damping added to the output filter in the average model
is strongly dependent on the type of relationship representation, i.e. algebraic o dynamic,
between Vcpk and IL as transient simulation results in Figs. 4.8 through 4.10 show. These
results, for parameter value Set 1 in Table 4, correspond to a switching model, a
simplified average model and the proposed average model. The simplified average model
uses a standard algebraic equation whereas the proposed average model approximates the
relationship between Vcpk and IL as dynamic through a single time constant equal to a
switching semi-cycle, Ts as shown in Fig. 4.7, i.e. IL is modified by a first order low pass
filter, whose output is labeled IL-slow in Fig. 4.7, before been used in the computation of
Vcpk according to (4.9) through (4.11).

Clearly the simulation results in Fig. 4.8 through 4.10 indicate that the proposed
average model closely tracks moving average of switching model state variables whereas
the simplified model presents poor tracking due to its faster dynamics, i.e. equivalent pole
frequency and damping factor higher than actual ones. Only usefulness of the average
model with the dynamic constraint will be thoroughly verified through transient
simulations for different parameter set values.

108
 Standard Approach Proposed Model

Figure 4.8. Filter inductor current (top) and capacitor voltage (bottom) from switching
(green), first average (blue) and second average (pink) models for parameter set 1 with
zero initial state for all models.

109
 Sta ndard Approach Proposed M odel

Sta ndard Approach Proposed and

Sw itching M odel

Sta ndard Approach Proposed M odel

Sta ndard Approach Proposed and

Sw itching M odel

Figure 4.9. Zoom in of filter inductor current and capacitor voltage from switching
(green), first average (blue) and second average (pink) models for parameter set 1 with
zero initial state for all models.

110
 Standard Approach Proposed Model

Figure 4.10. Zoom in of filter inductor current and capacitor voltage from switching
(green), first average (blue) and second average (pink) models for parameter set 1 with
zero initial state for all models.

111
4.3. Simulation Results

State variables from the average model with the dynamic constraint very closely
follow moving average of their respective counterparts in the switching model for
different parameter value sets (Table 4) as Figs. 4.10 through 4.25 show.

Table 4. Parameter set values for transient simulations.

Parameter Set 1 Set 2 Set 3 Set 4 Set 5 Set 6

Turns
6 4 4 4 6 4
Ratio
Leakage
1 uH 2uH 2uH 2uH 1uH 1uH
Inductance
Blocking
1uF 0.5uF 0.5uF 0.5uf 1uF 2uF
Capacitor
Filter
2uH 8uH 8uH 3uH 2uH 2uH
Inductance
Filter
200uF 50uF 50uF 33uF 200uF 50uF
Capacitor
Load
Resistance 1.1 Ω 1.1 Ω 3Ω 1.8 Ω 0.3 Ω 1.1 Ω
Saturable 60 µ V-s 60 µ V-s 60 µ V-s 60 µ V-s 60 µ V-s 60 µ V-s
Reactor

4.3.1. Transient simulations for parameter set 1

Simulations results for set 1 are shown in Figs. 4.11 through 4.14. This set of
parameters was calculated in a specific application design [20]. The load here was
selected to obtain a very lightly damped response with large oscillation amplitude while
still maintaining CCM operation since these conditions fully test the CCM model. State
variables of the proposed average model almost perfectly match the dynamics, i.e. pole
frequency and damping factor, of switching-model state-variable moving average for a
time interval over twenty times larger than the oscillation period, which is around
150 µ s. The oscillation amplitude of the average filter inductor current over the same
interval changes from 15A to 0.2mA, i.e. attenuation of 97dB. It is important to point out
that simulation time for the average model is still less than one tenth of that required by
the switching model for this type of agreement. The difference in pole oscillation
frequency between average model and switching model is around 1% according to the
phase difference seen at the end of the simulation interval in Fig. 4.14, i.e. phase shift less
than one quarter of a cycle after 20 cycles.

112
 Average Model

Average Model

Average and
Switching Model

Figure 4.11. Whole transient and zoom in of filter inductor current and capacitor
voltage from switching (green) and second average (pink) models for parameter set 1
with zero initial state for both models.

113
 Average Model

Average and
Switching Model

Average Model

Average and
Switching Model

Figure 4.12. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero initial state for
both models.

114
 Average Model

Average and
Switching Model

Average Model

Average and
Switching Model

Figure 4.13. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero initial state for
both models.

115
 Switching Model Crest Envelope

Average Model

Switching Model Valley Envelope

Switching Model Crest Envelope

Average Model

Switching Model Valley Envelope

Figure 4.14. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 1 with zero initial state for
both models.

116
 Moving average of filter inductor current was not calculated because of the
excellent agreement in output voltage. In other words, the only way for the capacitor
voltage in the average model to almost perfectly follow the moving average of the
capacitor voltage in the switching model is by receiving the same average filter inductor
current since the resistive loads are equal.

4.3.2. Transient simulations for parameter set 2

Simulations results for set 2 are shown in Figs. 4.15 and 4.16. All the parameter
values are different from those in set 1 but the load, which remained at 1.1 ohms.
Moreover these parameters were selected to produce a less lightly damped response than
the previous one with the same pole frequency. Consequently deep CCM operation is
seen. Again state variables of the proposed average model very closely match the
dynamics, i.e. pole frequency and damping factor, and steady state of switching-model
state-variable moving average over the transient interval and the subsequent time
respectively. Simulation time for the average model is again less than one tenth of that
required by the switching model for this type of agreement. Difference in output-voltage
steady-state values between models is less than 1%.

4.3.3. Transient simulations for parameter set 3

Simulations results for set 3 are shown in Figs. 4.17 through 4.19. All the
parameter values are the same as those in set 2 but the load, which changed to 3 ohms.
Naturally a more lightly damped response than the previous one is obtained but deep
CCM operation is still seen. Once again state variables of the proposed average model
very closely match the dynamics, i.e. pole frequency and damping factor, and steady state
of switching-model state-variable moving average for a time interval over twenty times
larger than the oscillation period, which is around 150 µ s. It is important to point out that
simulation time for the average model is still less than one tenth of that required by the
switching model for this type of agreement. The difference in pole oscillation frequency
between average model and switching model is around 1% according to the phase
difference seen at the end of the simulation interval in Fig. 4.19, i.e. phase shift less than
one quarter of a cycle after 20 cycles.

4.3.4. Transient simulations for parameter set 4

Simulations results for set 4 are shown in Figs. 4.20 and 4.21. Output filter
component values and load resistor value are reduced with respect to those in set 3 so that
the response is almost critically damped. Similarly to the previous cases average
dynamics is very closely matched and simulation time for the average model is still less
than one tenth of that required by the switching model for this type of agreement. Output
voltage steady state error is again less than 1%.

117
 Average Model

Average and
Switching Model

Figure 4.15. Whole transient filter inductor current and capacitor voltage from
switching (green) and second average (pink) models for parameter set 2 with zero
initial state for both models.

118
 Average Model

Average and
Switching Model

Average Model

Switching Model

Switching Model

Average Model

Figure 4.16. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 2 with zero initial state for
both models.

119
 Average Model

Average and
Switching Model

Figure 4.17. Whole transient of filter inductor current and capacitor voltage from
switching (green) and second average (pink) models for parameter set 3 with zero
initial state for both models.

120
 Average Model

Average and
Switching Model

Average Model

Switching Model

Average Model

Figure 4.18. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 3 with zero initial state for
both models.

121
 Average Model

Switching Model

Average Model

Average Model

Average Model

Figure 4.19. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 3 with zero initial state for
both models.

122
 Average Model

Average and
Switching Model

Average Model

Average and
Switching Model

Figure 4.20. Whole transient and zoom in of filter inductor current and capacitor
voltage from switching (green) and second average (pink) models for parameter set 4
with zero initial state for both models.

123
 Average Model

Switching Model

Average Model

Average Model

Switching Model

Switching Model

Average Model

Figure 4.21. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 4 with zero initial state for
both models.

124
4.3.5. Transient simulations for parameter set 5

Simulations results for set 5 are shown in Figs. 4.22 and 4.23. All the parameter
values are the same as in set 1 except for load resistor which gets reduced to 0.3 ohms.
The same as for set 1 average dynamics is almost perfectly matched and simulation time
for the average model is still less than one tenth of that required by the switching model
for this type of agreement.

4.3.6. Transient simulations for parameter set 6

Simulations results for set 5 are shown in Figs. 4.24 and 4.25. Except for leakage
and filter inductance values all the parameter values are changed. The same as for set 6
average dynamics is almost perfectly matched and simulation time for the average model
is still less than one tenth of that required by the switching model for this type of
agreement.

4.4. Dynamics Comparison among Buck, ZVS-FB and ZVZCS-FB

Converters

4.4.1. Transient response and small-signal transfer function from new average
model and its linearization

Results from linearization and their respective transient simulations, already

presented in Chapter 3, are reproduced here in Figs. 4.26 through 4.29 for further
analysis.

As already pointed out in Chapter 3 transfer functions in Figs. 4.27 and 4.29 show
that the amount of damping added to output filter and of reduction in its pole frequency
depends on parameters values and/or operating conditions for both ZVS-FB and ZVZCS-
FB converters. With parameter value Set I both soft-switched converters change the
damping factor by a fairly large amount albeit in opposite directions. For the other
parameter value set the ZVZCS-FB converter exerts a very small reduction in damping
whereas the ZVS-FB converter introduces a large increment.

Transient responses in Fig. 4.26 for parameter Set I show that voltage conversion
ratio, i.e. output voltage, is larger in the ZVS-FB converter whereas Fig. 4.28 shows the
opposite for parameter Set II.

From these observations it looks likely for the ZVZCS-FB converter to add either
positive or negative damping to the output filter depending on parameter values and
operating conditions as Appendix C explains in more detail.

125
4.4.2. Small-signal experimental results

Figure 4.30 shows experimental voltage to output transfer function for Buck and
ZVZCS-FB converters for parameter value Set I. Peaking for ZVZCS-FB converter is
higher than that for the Buck converter as predicted by the small-signal average model.
Differences between experimental and simulation results are mostly due to idealization of
components, i.e. neglect of parasitics, hysteresis and tolerances.

126
 Average Model

Average and
Switching Model

Average Model

Average and
Switching Model

Figure 4.22. Whole transient and zoom in of filter inductor current and capacitor
voltage from switching (green) and second average (pink) models for parameter set 5
with zero initial state for both models.

127
 Average Model

Switching Model

Average Model

Switching Model Average Model

Switching Model

Average Model

Figure 4.23. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 5 with zero initial state for
both models.

128
 Average Model

Average and
Switching Model

Average Model

Average and
Switching Model

Figure 4.24. Whole transient and zoom in of filter inductor current and capacitor
voltage from switching (green) and second average (pink) models for parameter set 6
with zero initial state for both models.

129
 Average Model

Switching Model

Average Model

Switching Model Average Model

Switching Model

Average Model

Figure 4.25. Zoom in of filter inductor current and capacitor voltage from switching
(green) and second average (pink) models for parameter set 6 with zero initial state for
both models.

130
 B uck
Z V S -F B

Z V Z C S -F B

Z V Z C S -F B

B u ck

Z V S -F B

Figure 4.26. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVS-FB (blue) and ZVZCS-FB
(black) converters with parameter set I.

131
 ZVZCS-FB Buck

ZVS-FB

Buck

ZVS-FB

ZVZCS-FB

ZVZCS-FB Buck

ZVS-FB

Buck

ZVS-FB

ZVZCS-FB

Figure 4.27. Control to capacitor voltage (top) and control to filter inductor current
(bottom) transfer functions from new average models for Buck (red), ZVS-FB (blue)
and ZVZCS-FB (black) converters with parameter set I.

132
 Buck

ZVZCS-FB

ZVS-FB

Buck

ZVZCS-FB

ZVS-FB

Figure 4.28. Capacitor voltage (top) and filter inductor current (bottom) transient
response from new average models for Buck (red), ZVS-FB (blue) and ZVZCS-FB
(black) converters with parameter set II.

133
 ZVZCS-FB
Buck

ZVS-FB

Buck

ZVS-FB

ZVZCS-FB

ZVZCS-FB Buck

ZVS-FB

Buck

ZVS-FB

ZVZCS-FB

Figure 4.29. Control to capacitor voltage (top) and control to filter inductor current
(bottom) transfer functions from new average models for Buck (red), ZVS-FB (blue)
and ZVZCS-FB (black) converters with parameter set II.

134
 50
ZVZCS

40
Magnitude (db)

30
BUCK
20

10

60

0
ZVZCS
Phase (deg)

-60 BUCK

-120

1 10 100

Frequency (kHz)

Figure 4.30. Experimental control to capacitor voltage (top) transfer for Buck and
ZVZCS-FB converters with parameter set II.

135
5. MODELING AND MODULATION FOR QSS-ZVZCS
THREE-PHASE BUCK RECTIFIER

The new procedure and the average model for the ZVZCS-FB-PWM dc-dc
converter from the previous chapter are extended here to develop a counterpart for the
Quasi-Single-Stage (QSS) ZVZCS three-phase buck rectifier shown in Fig. 5.1(a).
Average steady-state operation occurs over one line voltage cycle, e.g. 60Hz, and hence
average along the switching frequency orbit to obtain autonomous average model, as in
previous chapters, no longer applies. Nevertheless, the average model still can represent
most of the rectifier’s dynamics and can be used for stability analysis.

Assuming that closed-loop bandwidth dynamics is much faster than line

frequency allows us to consider the QSS-ZVZCS rectifier as operating in a quasi-steady-
state tracking condition. This new average model revealed strong nonlinear relations
between applied and effective duty-cycles of standard space vector modulation (SVM).
Those nonlinearities are the source of increased input current distortion and output
voltage ripple. If these were left to be solely counteracted by the feedback loop, the latter
would have to exhibit very large bandwidth, which is already constrained by the
switching frequency.

Based on insight provided by the development of the average model, a new

modulation scheme together with feed-forward duty-cycle compensation is proposed to
effectively minimize output voltage ripple with slight ac current distortion, while
allowing use of the same single-loop control strategy. Experimental results verify average
model predictions as well as modulation and duty-cycle compensation scheme efficacy.

5.1 Three-Phase Buck Rectifier

Operation of the three-phase PWM buck rectifier, Fig. 5.2(a) is reviewed first to
help desription of its synchronization with the ZVZCS-FB converter.

According to the nature of the input and output variables (currents and voltages)
and the direction of energy flow, three phase converters can be classified as current
source or voltage source rectifiers or inverters. The input variables of the buck rectifier
are the three phase input voltages and the dc current source. The output variables are the
dc link voltage and the three-phase AC input currents. Hence the buck rectifier can be
also viewed as a Voltage Source Rectifier. The process of synthesizing the low frequency
output variables of the converters could be described as follows [H3, N3]:

136
 p
Lf
D1
N:1
S1 S3 +
S ap Sbp S cp +
Vs I Lf
L sa Vo
C blk L lk - -

x y
Ip
S2 S4
San S bn Scn D2

137
n
Va Vb Vc

Buck Rectifier ZVZCS- FB Converter

(SVM) (Phase Shifted Modulation)

Fig.5.1. QSS-ZVZCS three-phase rectifier

 p
Sap Sbp Scp
Va ia
ib
Vb ic I
Vc
San Sbn Scn

n
a) Simplified three-phase buck rectifier structure

Sbn Sap Scn Sbp San Scp

va vb vc

600 1800 3000

00 0
120 2400

Sector 6 Sector 1 Sector 2 Sector 3 Sector 4 Sector 5

b) Input phase voltage determines 600 electric sectors and the corresponding
switch that is always-on throughout the sector

Fig. 5.2. Three-phase buck rectifier and electric sectors.

138
 For a set of input voltages,

v a = Vm cos( ωt + ϕ ),
vb = Vm cos( ωt − 2π 3 + ϕ ), (5.1)
vc = Vm cos( ωt − 4π 3 + ϕ ),

output current,

io = I , (5.2)

desired set of input currents,

ia = I m cos( ωt + θ ),
ib = I m cos( ωt − 2π 3 + θ ), (5.3)
ic = I m cos( ωt − 4π 3 + θ ),

and desired dc link voltage,

Vout = V pn , (5.4)

determine the control law requirements for the switches of the front-end rectifier.

The six-step modulation of the three-phase PWM buck rectifier is described in the
following with reference to Fig. 5.3. Due to voltage sources on the AC side and current
sources on the DC side of the rectifier, the converter switches can assume only six
allowable combinations that yield non-zero phase currents and three combinations that
yield zero phase currents. In space vector representation, the input phase currents are
therefore synthesized from 7 discrete current vectors I0 to I6, also called current switching
state vectors (SSVs). The set of SSVs that yield non-zero phase currents form the VSR
hexagon as shown in Figure 5.3(a). The parenthesized symbols in the VSR Hexagon
represent the switches that are conducting during the synthesis of the respective current
vector. The triangular area between two adjacent space vectors is called a sector and it is
analog to the sectors in Fig. 5.2 (b). The space vector of the desired phase currents iref,
called the reference vector, can be synthesized as a time weighted average of the two
adjacent non-zero SSVs and an appropriate zero SSV over a switching cycle Ts. Since
the operation of the converter within the sectors has circular symmetry, the duty cycles of
the three SSVs belonging to a sector that are used for the synthesis of the reference vector
over a switching cycle are given by:

d 1 = m ⋅ sin( 60 0 − θ i ),
d 2 = m ⋅ sinθ i , (5.5)
d0 = 1 − d1 − d 2

139
 I3 (Sbp , Scn )
duty cycle ii
I4 (Sbp , San ) 3 2 I2 0.866
I2 (Sap , Scn ) d 2I 2
Io 1 0.5
4
iref iref
d1 I θi
5 6 1
I1 (Sap , Sbn ) I1
I5 (Scp , San) duty cycle i
0
00 θi 600
I6 (Scp , Sbn )

b) Normalized duty-cycle variation

a) SVM hexagon and vector synthesis
within electric sector 1

140
I1 I2 I0
p p p
Sap Sbp Scp Sap Sbp Scp Sap Sbp Scp
Va ia ib Va ia Va ia ib
ib ic
Vb ic I Vb ic Vb I
I
Vc Vc Vc
San Sbn Scn San Sbn Scn San Sbn Scn

n n n

a) Circuit topologies for electric sector 1

Fig.5.3. Three-phase buck rectifier with standard SVM

 10 d1 d2
0 ib IfL
0
Phase
10 Currents
ic
-10
0.5
0
-0.5 ia
b) Ideal phase currents (Amp)
and output voltage ripple (Volt) Vo

141
.867
d1 Vpn Vab
Rail
0 Voltage Vac
.867

d2
0
60 0
c) Pulsed waveforms
a) Normalized duty cycles

Fig.5.4. Three-phase buck rectifier ideal SVM operation

where d1, d2 and θi are shown in Figure 5.3(a) and (b) and 0<m<1 is the modulation
index. In this standard SVM operation, the same SSV is applied first throughout the
sixty-degree sector as indicated in Figs. 5.3(b) and (c). The major advantage of this
modulation scheme is smooth moving average of the phase currents and output voltage.

With these duty cycles and fixed m and the current source value I, the local
averages of the phase currents are sinusoidal (5.3), and the average voltage Vpn is dc as
desired, Fig. 5.4(a),

3
V pn = ⋅ m ⋅ Vm . (5.6)
2

The sectors of the VSR hexagon shown in Figure 5.3(a) correspond directly to the
60 -sector within the period of the desired phase currents. The angle θi in (5.5) and
0

Fig. 5.3(a) and (b) is the angle within the sector, and the duty cycles d1 and d2 can then be
expressed as:

i1
d1 = m ⋅ ,
I (5.7)
i
d2 = m ⋅ 2 ,
I

where i1 and i2 are the two phase currents that have the same sign within the current 600
segment. It should be noted that SSV duty cycles given by (5.7) are not the duty cycles
of the individual switches but of the switching combinations that realize the same. Also
the term normalized duty-cycles used in Figs. 5.3, 5.4 and 5.6 denotes duty-cycles with
m = 1.

5.1.1. Three-phase buck rectifier average model

The average circuit model for the three-phase buck rectifier shown in Fig. 5.5
[H3, N3] can also be easily obtained with the procedure given above by starting with the
circuit topologies and pulsed waveforms shown in Figs. 5.3 and 5.4. The current source I
is assumed constant during a switching cycle, i.e. no ripple, and the sector duty-cycles are
given by (5.5). The quantities da, db and dc represent ac phase-current duty-cycles,
d a = d ap − d an , d b = d bp − d bn , d c = d cp − d cn , whereas dab, dbc and dca correspond to line-
voltage duty-cycles, d ab = d ap − d bp , d bc = d bp − d cp , d ca = d cp − d ap . The former are the
individual contributions of I to ia, ib and ic and the latter are the individual contributions
of instantaneous Vab, Vbc and Vca to the rail voltage, Normalized values for phase current
and line voltage duty-cycles are represented by the solid traces in Fig. 5.13(a) and (b)
respectively for a whole line cycle with SVM operation. Since there is no neutral
connection, the sum of the three-phase currents is zero at any time and hence the sum of
their duty-cycles must equal zero.

142
 da ⋅ I vab
va dab ⋅
N +
+
db ⋅ I vbc +

143
vb dbc ⋅ v pn
N I
+
dc ⋅ I v −
vc dca ⋅ ca
N

Fig.5.5. Three-phase buck rectifier average model structure

 I1 I2 I0 I1 I2 I0 I1 I2 I0 I2 I1 I0

duty cycle ii duty cycle i

0.866 0.866

0.5 0.5

144
duty cycle i duty cycle ii
0 0
00 60 0 00 60 0
θ 30 0 30 0 θi
i

a) Normalized duty-cycle variation b) Normalized duty-cycle variation

and SSV sequence within electric and SSV sequence within electric
sector 1 for standard SVM sector 1 for SVM with swapping

Fig.5.6. Three-phase buck rectifier SVM with and without swapping

5.1.2. Three-phase buck rectifier with single-loop control

According to (5.5) and (5.7) the modulation index can be varied to control phase
currents and rail voltage. When only the modulation index is changed to regulate the
output voltage, the control becomes single-loop type, which is the one used in our
application. The other parameter that can be changed in the sector duty-cycles, for our
control scheme, while still producing sinusoidal phase currents, is the phase shift, i.e.
instead of 60 o and 0 o in (5.5) a feedback dependent angle may be added to the argument
in the sine function. This allows control of input displacement factor and turns the control
into a two-loop type.

5.1.3. Modified SVM (swapping)

A modified SVM operation, named duty-cycle swapping from here on, and shown
in Fig. 5.6, swaps the order of application of the duty-cycles in the middle of the
60 o electric sector so that the larger duty-cycle always appears first in a switching period.
Effects of this modulation scheme on the phase currents and output voltage are discussed
later in the chapter.

5.2. QSS-ZVZCS Three-Phase Buck Rectifier Operation

5.2.1. Three-phase buck rectifier and ZVZCS-FB converter synchronization

When the three-phase buck rectifier and the ZVZCS-FB converter get directly
connected (no energy storage components in between them) to form the QSS rectifier
shown in Fig. 5.1, the switching transitions must be carefully synchronized to obtain
proper operation of the whole system.

According to Fig. 5.3(c), when non-zero SSVs are selected, the current source I is
connected between two phase-voltages. The ZVZCS-FB converter simulates this current
source by connecting reflected filter inductor current, ILf, to the rails p and n when
diagonally opposed full-bridge switches get activated, Fig. 5.7(a). For the zero SSVs
interval either top or bottom switches in the full-bridge are activated, Fig. 5.7(b). This
disconnects the current source from the ac voltages and takes full advantage of ZVZCS-
FB converter characteristics [W2], e.g. reduced conduction losses since fewer switches
are connected in series, zero-current switching for some devices in the front-end buck.
Furthermore, to produce balanced driving of the transformer duty cycles of switch
combinations in the front-end buck rectifier are kept the same for positive and negative
primary-side semi-cycles, as shown in Fig. 5.8.

5.2.2. QSS-ZVZCS three-phase buck rectifier operation with standard SVM

Figure 5.8 shows QSS-ZVZCS three-phase rectifier’s typical waveforms when the
ZVZCS-FB converter section operates in CCM. These waveforms correspond to Sector 1

145
 d1 d2 d0
p p p
Va Va Va
Vb I Vb I Vb I
Vc Vc Vc

n n n
p Lf p D1 Lf
N:1 + S1 S3 N:1 +
S1 + If +
Vs If Vo Vs
- - - Vo
-

Ip

146
Ip
S4 D2
D2
n
n
p Lf p D1 Lf
D1
N:1 N:1 +
S3 + + If +
Vs I f Vo
Vs
-
Vo
- -
-

Ip
Ip S2 S4
S2 D2
n
n
a) Non-zero phase current vectors a) Zero phase current vectors

Fig.5.7. Synchronization between three-phase buck rectifier and ZVZCS-FB converter

of input phase voltages in Fig. 5.2(b). In this chapter, only a brief description of CCM
waveforms relevant to the development of the averaged circuit model and its simplified
expressions for use in the duty-cycle compensation scheme are derived.

From Figs. 5.7 and 5.8 it is apparent that only 6 of the 10 switches are active
during a 600 sector. The 4 switches of the ZVZCS full-bridge are activated during every
sector and their sequence remains unchanged throughout the entire operating duration of
the converter. The switching sequence of the devices in the front-end buck rectifier is
decided by the respective SSVs that have to be made active to synthesize the reference
current vector.

5.2.3. Topological stages and analytical description

Figure 5.8 describes the CCM operation of the converter through equivalent
circuit structure for each switch configuration interval as well as waveforms for bus and
bridge voltage, Vpn and Vab, primary current, Ip, bus current, Ibus, blocking capacitor
voltage, vcb, filter inductor current, If and, output and secondary rectifier’s voltage, V0 and
Vs.
Assume the switching cycle starts with the blocking stage at to (beginning of d1)
when bridge voltage Vxy becomes positive and the saturable reactor blocks any primary
current, and ends at t1 when the reactor gets saturated. The sum of input line voltage Vab
(for Sector 1 in Fig. 5.2) and blocking capacitor voltage determines the rate of change of
the flux in the saturable reactor. The change of flux is

 Vline1 + Vcpk  V + Vcpk 

∆φblk = (t1 − t0 ) ⋅   = ⋅(Dblk ⋅ Ts ) ⋅  line 2  , (5.8)
 N sr   N sr 

where Dblk, Nsr and Vcpk are the blocking stage duty-ratio, saturable reactor number of
turns and peak blocking capacitor voltage. On the secondary side, the rectifier output
voltage determines the rate of change in the filter inductor current.

During charging stage, (t1,t2), the same rate of change applies to filter inductor
current, whereas the change in primary current, after neglecting transformer’s
magnetizing current,
 Vline1 + Vcpk 
I 2p =  (t 2 − t1 )⋅ = (m1) ⋅ (Dch ⋅ Ts ) , (5.9)
 LLk 

where slope m1, shown in Fig. 5.8(a), is defined by the first bracket, Dch corresponds to
the charging stage duty ratio and the remaining quantities are defined in Fig. 5.8(a).

147
 Llk /N 2 Lf

Off
VSA Blocking

Blocking
Resetting

Charging
Transfer 2

Transfer 1
V1 /N
I
Ibus /N If
Vxy Vs V0 RL
2
Llk /N Lf Charging
d1 Ts d2 Ts do Ts
V1 /N
Ibus /N If
Vs V0 RL
f I 3p I 4p
I 2
2
Ip m3 Llk /N Lf
m1 m2 Transfer-1
V1 /N If
Ibus /N
Vs V0 RL

Llk /N2 Lf
f f Transfer-2
I 3 I 4 V2 /N

148
N ⋅ m2 Ibus /N If
If m4 Vs V0 RL

m4 Llk /N2 Lf
I 2f If f
Resetting
I 5 VCblk /N
ICir /N If
Vs V0 RL

Vo V Line1 N VSA Llk /N 2 Lf

Off
Vs V Line2 N VCblk /N
ICir /N If
Vs V0 RL
t0 t1 t2 t3 t4 t5 t6 t
t0 +TS

a) Typical waveforms in CCM Case 1 b) Switch structures in CCM Case 1

Fig.5.8. QSS-ZVZCS rectifier typical waveforms and switch structures

 At time instant t2, primary current and filter inductor current are related by
transformer’s turns ratio, i.e.

I 2f = I 2p ⋅ N , (5.10)

and they remain so through transfer stage 1. The latter ends at t3 with first commanded
duty-cycle d1, when the buck rectifier selects line voltage Vac, for sector 1 in Fig. 5.2(b)
i.e.

d 1 ⋅ Ts = (t 3 − t0 ) = (Dblk + Dch + Dtrf 1 ) ⋅ Ts . (5.11)

Reflection of input line voltage and transformer leakage inductance to the

secondary side leads to the equivalent circuits shown in Fig. 5.1(b) for this transfer stage.
Change in the filter inductor current, after neglecting blocking capacitor effects, is
approximately given by

 Vline1 
 −V 
 ⋅ (t 3 − t 2 )⋅ = ( N ⋅ m2 ) ⋅ (Dtrf 1 ⋅ Ts ) ,
I −I =
f f N 0 (5.12)
3 2
 Llk 2 + L f 
 N 

where slope N ⋅ m2 is defined by the first bracket and the other terms by Fig. 5.8.

Duration of transfer stage 2 is directly second commanded duty-cycle d2 and the

change in the filter inductor current is given by

 Vline 2 
 −V 
 ⋅ (t 4 − t 3 )⋅ = ( N ⋅ m3 ) ⋅ (d 2 ⋅ Ts )
I −I =
f f N 0 (5.13)
4 3
 Llk 2 + L f 
 N 

where slope N ⋅ m3 is defined by the first bracket and the other terms by Fig. 5.8(a).

Resetting stage starts at t4, when bridge voltage Vxy becomes zero and it ends
when primary current does the same at t5. Duration of this stage is given by

1  Ip Llk 
t 5 − t 4 = Dres ⋅ Ts = ⋅ arcsin 4 ⋅ . (5.14)
LLk ⋅ C Blk  
 VCpk Cblk 

Off stage begins at t5 when saturable reactor blocks any primary current by taking
Vcpk as its flux rate of change and it ends at (to + Ts) the with primary switching semicycle
when Vxy becomes negative as shown in Fig. 5.8(a).

149
 iL
d̂a ⋅ Lf
va N ~ v
dab ⋅ ab
N +
iL + iL
d̂b ⋅ RL

150
N ~ v +
vb + vS
dbc ⋅ bc
N vo C
iL + VCx
d̂c ⋅ −
N ~ v
vc dca ⋅ ca +
N

Fig.5.9. QSS-ZVZCS PWM rectifier average model structure

 During this stage the change in flux across the saturable reactor is given by

Vcpk ⋅ (1 − d 1 − d 2 − Dres ) ⋅ Ts
∆ φoff = , (5.15)
N sr

which together with saturable reactor volt-second blocking capability determines

blocking stage duration, i.e.

∆ φblk = 2 ⋅ φ sat − ∆ φoff , (5.16)

where ∆ φblk is given by (5.8).

Expressions for peak blocking capacitor voltage, Vcpk , and average filter inductor
current I L , are calculated next to complete the set of equations and the same approxi-
mation to calculate VCpk value followed in Chapter 4 is used here. That is, looking at
converter’s steady-state operation and taking into consideration relevance of stage’s
duration upon change in capacitor voltage. These voltage changes during transfer and
resetting stages are respectively given by

I L ⋅ (Dtrf 1 + d 2 ) ⋅ Ts
∆ Vc −trf = (5.17)
N ⋅ C blk
and

∆ Vc − res =
(I )4
f 2
⋅ Llk
, (5.18)
N ⋅ IL ⋅ (D trf 1 + d 2 ) ⋅ Ts

From Fig. 5.8, after neglecting the voltage change during charging stage, VCpk is given by

∆ Vc−trf + ∆ Vc−res
Vcpk = . (5.19)
2

On the other hand, IL is calculated as

IL =
1
2
[ ( ) ( )
⋅ Dtrf 1 ⋅ I 3f + I 2f + d 2 ⋅ I 4f + I 3f + (1 − Dtrf 1 − d 2 ) ⋅ I 5f + I 4f ,( )] (5.20)

where

V 
(I 5
f
)
− I 4f =  0
L
 ⋅ (1 − Dtrf 1 − d 2 ) ⋅ Ts = m4 ⋅ (1 − Dtrf 1 − d 2 ) ⋅ Ts ,

(5.21)
 f 

with slope m4 defined by the term in the first bracket and Fig. 5.8(a).

151
Vcpk

A2
0
A1

-Vcpk
(Dtrf1 + D2) TS

A1 A2 --
Vcb =
(Dtrf1 + D2) TS

Fig. 5.10. Calculation of average blocking capacitor voltage.

152
5.3. New Average Circuit Model for the QSS-ZVZCS Rectifier

An input-output structure for the average model of the QSS-ZVZCS rectifier is

shown in Fig. 5.9. This structure has been obtained by following the new procedure as in
Chapter 4 and in Section 5.1.1 together with the assumption of quasi-steady state
operation. The starting point is the circuit topologies and pulsed waveforms shown in
Fig. 5.8. A detailed derivation is presented below.

5.3.1. Step 1: Fast/slow classification of state variables

Figures 5.8 indicates that filter inductor current and output capacitor voltage
should be considered slow variables in CCM and used as states in the average circuit
model, similarly to Chapter 4.

Once again, the primary current is discarded as a relevant average state variable
because its moving average is zero in steady state operation and exhibits large
components at one half the switching frequency and higher harmonics during transient
regime.

The blocking capacitor voltage waveform in Fig. 5.8 indicates that it must be
classified as a fast variable that belongs to an energy holding element. Its treatment here
is the same as is the previous chapter, i.e. its effect on peak blocking capacitor voltage is
modified by a time constant.

5.3.2. Step 2: LTI input/output parts

Output filter and three-phase input phase voltage sources get selected as LTI
networks according to circuit topologies in Fig. 5.8(b).

5.3.3. Step 3: “Independent” variable drawn from LTI input network and
“Dependent” variable delivered to LTI output network

From Figs. 5.1 and 5.8 it looks apparent that average phase currents are the
“dependent variables” drawn from the three-phase voltage sources, whereas secondary
rectifier’s output voltage is the “independent variable” applied to the output filter during
CCM operation.

5.3.4. Step 4: Calculation of one-cycle average for the variables in the previous step

For the average model in Fig. 5.9 the quantities d̂ a , d̂b and d̂ c represent ac
phase-current duty-cycles or equivalent primary duty-cycles as defined in Fig. 5.12,
~ ~ ~
whereas d ab , d bc and d ca correspond to line-voltage duty-cycles or equivalent secondary
duty-cycles as defined in Fig. 5.12. The former are the individual contributions of
reflected filter inductor current to ia, ib and ic and the latter are the individual
contributions of reflected instantaneous Vab, Vbc and Vca to the secondary rectifier voltage.

153
 d1 d2
10 A
ia
0
d1- pri
-10
-10 A
10 A
ib
0
ic
-10 A

0.5 V

154
0
-0.5 V

1.0 V
Vo
Vs
0

-1.0 V
d1- sec

a) Waveforms for ideal buck and b) Applied and effective duty-

experimental ZVZCS rectifiers cycles for ZVZCS rectifier

Fig.5.11. QSS-ZVZCS rectifier desired and experimental waveforms with typical SVM
operation
 If
N
i1 i1 i1
d1 d2 d2
If If If
d1-pri
i2 N N N
i2 i2
d2-pri d2-pri

-(i1+i2) -If -(i1+i2) -If

-If
VLine1+VCblk N N VLine2+VCblk
N
VLine2+VCblk
N

155
VLine2+VCblk N N
Vs Vs Vs
N
d1 d2-sec d1 d2-sec
d1-sec d2

a) Case 1 b) Case 2 b) Case 3

Fig.5.12. QSS-ZVZCS rectifier equivalent primary and secondary duty-

cycles cases with typical SVM operation
Normalized values for phase current and line voltage duty-cycles are represented by the
dashed traces in Fig. 5.13(a) and (b) respectively for a whole line cycle with SVM
operation.

Figure 5.12 shows three different cases for equivalent primary and secondary
duty-cycles cases based upon duty-cycle loss. In Case 1, Fig. 5.12(a), the loss of duty-
cycle occurs only in the first duty-cycle both in primary and secondary side, e.g. when the
first commanded duty-cycle has a large value, i.e. at the beginning of the sixty-degree
electrical sector. In Case 2, the loss of duty cycle occurs in both first and second duty-
cycles, Fig. 5.12(b), e.g. near the end of the electric sector. Moreover, the first secondary
duty-cycle becomes zero and stays the same for Case 3 when first primary duty-cycle
also becomes zero as shown in Figs. 5.12(c) and 5.13.

One-cycle average calculation of the controlled sources is derived next for Case 1
in Fig. 5.12. Modified equations for the other cases are given in Appendix D.

According to Fig. 5.8, the secondary rectifier voltage is a function of blocking

capacitor voltage Vcb , output and line voltages during transfer stages 1and 2, i.e.

Vline1 + Vcb L
⋅ L f + V0 ⋅ lk2
Vs 1 = N N (5.22)
Llk
+ Lf
N2
and

Vline 2 + Vcb L
⋅ L f + V0 ⋅ lk2
Vs 2 = N N , (5.23)
Llk
+ Lf
N2

where Vline1 and Vline2 are the line voltages applied during duty-cycles d1 and d2
respectively to the full-bridge by the front-end buck rectifier. Secondary rectifier voltage
is zero during the rest of the switching semi-cycle. From (5.22), (5.23) and Fig. 5.8 the
one-cycle average rectifier voltage can be expressed as

(V
line 1 ⋅ Dtrf 1 + Vline 2 ⋅ D2 )  L V
⋅ L f + V0 ⋅ lk2 + cb ⋅ L f

 ⋅ (Dtrf 1 + D2 )
N N N 
Vs =   (5.24)
Llk
+ Lf
N2

156
where Vcb is the average of blocking capacitor voltage during transfer stages. Vcb is,
according to Fig. 5.10, directly proportional to the difference between areas A2 and A1,
i.e.

I L ⋅ (Dtrf 1 + D2 ) ⋅ TS
Vcb = Vcpk − . (5.25)
2 ⋅ N ⋅ Cblk

Figures 5.4, 5.8, 5.11 and 5.12 indicate that each controlled current source
corresponds to one-cycle average phase current and that average first and second phase
currents Iphase1 and Iphase2 can be computed as

I phase1 =
I 2p
⋅ Dch + 2
(
I p + I 3p
⋅ Dtrf 1
) (5.26)
2 2

and

I phase 2 =
(I 3
p
+ I 4p )
⋅ d2 . (5.27)
2

In the simulations, the calculation of Dtrf1 is again carried out on-line in the
simulator by closing the loop around operational amplifiers to find the root located
between 0 and d1. Equations (5.1) through (5.27) can be combined to find an expression
with Dtrf1 as the only unknown or they can be arranged to solve for as many of unknown
quantities as desired.

5.3.5. Step 5: Calculation of algebraic constraints

These constraints have been already described in Section 5.2.2 by (5.1) through
(5.14) for Case 1 in Fig. 5.12. Modified equations for the other cases are given in
Appendix D.

5.3.6. Step 7: Implementation of circuit oriented simulation

The same analog techniques used in the previous three chapters can applied here
to compute Dtrf1 in real time during the simulation. The small differences arise in the
number of equations and boundary conditions for the different cases in Fig. 5.12.

5.3.7. Modeling of energy holding elements in fast dynamic subsystems

The same heuristic approach followed in Chapter 4 for the dynamic relation
between average filter inductor current and peak blocking capacitor voltage is used here
for large signal transient simulations. However, the analysis is instead oriented towards
identification of ac input current distortion and output voltage ripple origins, as well as
their correction.

157
 0.5
da 0.5 dab

0 0

-0.5 -0.5

0.5 db 0.5 dbc

0 0

-0.5
-0.5

0.5 0.5

158
0 0
dc
-0.5 dca
-0.5

00 600 1200 1800 2400 3000 00 600 1200 1800 2400 3000

a) Primary b) Secondary

Fig.5.13. Three-phase buck rectifier (solid) and QSS-ZVZCS rectifier simulated

effective (dashed) primary and secondary duty-cycles for whole line cycle with SVM
 Effective d2-desired
0.866 duty cycle 2 d1-eff
0.866 0.5
d1-compens d2 0
0.5
0.5 d2 d1
d1-desired 0
d1-desired 600
0.5 θi
00
0.22

159
Comp 0.12
Effective 200V
duty cycle 1 va 0V
0
0
0
200V
0 60 00
0 600 00 3600

a) Simulation: 60 degree sector b) Experimental: 1 line cycle

Fig.5.14. Normalized QSS-ZVZCS rectifier simulated and experimental duty-

cycles, compensation with SVM and phase voltage
5.4. Distortion Analysis

Ideally, the duty-cycles applied to two switches of the front-end buck rectifier, d1
and d2, are sinusoidal as shown in Figs. 5.3 and 5.4 whereas the switch corresponding to
the largest absolute phase voltage stays on for a 600 electric sector (Figs. 5.1, 5.3, 5.7 and
5.8). When pulsed phase currents and rail voltage are as in Fig. 5.4(c) their ideal moving
average values look like those in Fig. 5.4(b). Unfortunately, QSS-ZVZCS rectifier typical
pulsed waveforms, Fig. 5.8, for the same sinusoidal duty-cycles exhibit strong differences
from those in Fig. 5.4(c), which leads to the highly distorted filtered experimental phase
currents and large output voltage ripple in Fig. 5.11(a) and 5.15(a). These differences,
detailed in Fig. 5.11(b), are mainly caused by the loss of duty-cycle that affects effective
primary and secondary duty-cycles d1-pri and d1-sec in Fig. 5.12. As explained in Section
5.2.4 they are the equivalent contribution of filter inductor current and input line voltages
to input phase current and secondary rectifier voltage respectively. As the value for duty-
cycle d1 approaches zero at the end of the 600 sector, QSS-ZVZCS rectifier pulsed
waveforms suffer further changes as depicted in Fig. 5.12 and labeled Cases 2 and 3. In
the average circuit model shown in Fig. 5.9 d1-pri and d1-sec are replaced by equivalent
phase current duty-cycles (with caret) and equivalent secondary rectifier duty-cycles
(with tilde).

These nonlinear relations between commanded and effective primary and

secondary duty-cycles are illustrated in Fig. 5.13 for a full line cycle. Clearly the largest
perturbations in effective duty-cycles occur in the vicinity of the electric sector border.

5.5. Hardware implementation

Figure 5.16 shows control block diagram for the prototype whereas Fig. 5.17
presents power stage circuit diagram. Details for the former with standard SVM are
presented next.

The operation of the switches of the converter has to be synchronized with the
three phase input AC voltages. The present 600 sector in the input line cycle is
determined according to the polarity of the input phase and line voltages. This sector
information is coded into a six bit control word (Si0-Si5), where the lower three bits (Si0-
Si2) represent the polarities of the line voltages Vab through Vca, and the upper three bits
(Si3-Si5) represent the polarities of the phase voltages Va through Vc. The SSVs to be
applied to synthesize the reference current vector are determined from the control word.
The modulation index m, is supplied to the digital control algorithm from the error
amplifier network that implements the output voltage and inductor current loops. The
sinusoidal functions required for the determination of the duty cycles in Fig. 5.4 can be
obtained either from the input phase voltages by reading them through A/D converters or
from pre-stored look-up tables with the table read-out synchronized with the input phase
voltages. The latter approach is followed here in that the duty cycles are synchronously
derived from the look up tables to reduce number of A/D conversions. The
synchronization process is explained in detail in a later section. The duty cycles along

160
with the control word is then sent to the decoder logic, which distributes the switching
pulses to the respective switches with the appropriate duty cycles.

5.5.1. Implementation of digital controller

The block diagram of the controller hardware shown in Figure 4.16 indicates that
the digital controller is built around the ADSP-2101, a 16-bit fixed point digital signal
processor from Analog Devices Inc. The control board houses an 8-channel 8-bit A/D
converter, a 4-channel 8-bit D/A converter, an address decoder and an EPLD (Electrically
programmable Logic Device) from Altera Inc. The EPLD consists of the decoder logic
that derives the switching waveforms based on the sector information in the control word.
The controller uses two A/D converter channels to sample the voltage at phase a and a
square wave at 6 times the line frequency containing the zero cross information of all the
three phase voltages. This square wave is used to synchronize the six-step modulation
with the input phase voltages. The synchronization process is presented in a later section.
A third A/D converter channel is used to sample the modulation index m from the output
voltage and inductor current feedback loops. 2 PWM signals A and B, as determined
from the duty cycles read from the look-up tables, a synchronization signal S1 and the
control word are required for the generation of the switching waveforms for the devices.
These are supplied to the decoder logic built into the EPLD to determine the appropriate
switches to be turned on or off with their respective duty cycles. The signals from the
decoder are then fed to a digital interface board that incorporates the required turn-on and
turn-off delays for the individual switches before they are sent to the gate drive circuits.

5.5.2. Implementation of decoder logic

The decoder logic that generates the switching signals for all the switches of the
converter is implemented using an Electrically Programmable Logic Device (EPLD)
from Altera Inc. The decoder consists of an array of double buffered counters that are
used to generate the main PWM signals A and B. It also consists of a sampling clock
generated by dividing the system clock. The sampling clock is also used to generate the
interrupt to the DSP to enable sampling the analog inputs at regular intervals. In
addition, the decoder contains the combinatorial logic blocks implemented to determine
the switching instants of the switches of the ZVZCS bridge and of the front-end buck
rectifier from the control word generated from the signs of the input phase and line
voltages. The turn-on and turn-off delays for the switches are not implemented inside the
EPLD. A dedicated digital interface board is used to implement these delays. The EPLD
used is the Altera EPM-5192, which has 192 macrocells. The architecture of the decoder
logic is optimized such that the EPLD can be operated at a maximum system clock
frequency of 21.73MHz. This frequency limits the switching frequency of the converter
depending on the bit resolution used in the counters for producing the PWM signals.
With a counter frequency of 20MHz and a bit resolution of 8 bits the switching frequency
fs can be derived to be equal to 78kHz. This is the switching frequency at which the
converter is operated.

161
 200V/div va 200V/div

10A/div ic ,ia 10A/div

162
1V/div 1V/div
vo

5ms/div 5ms/div

a) Uncompensated b) Compensated

Fig.5.15. QSS-ZVZCS rectifier open-loop experimental phase voltage and currents and
output voltage ripple with SVM, before and after compensation for 360V peak line voltage,
48V output voltage and 40A load current
 GATE SIGNALS
...

DECODER
ALTERA EPM-5192

d 2* d 1* ADSP-2101
+
SECTOR

d2 d1

LOOK-UP TABLE DUTY-CYCLE

COMPENSATION

φ
COUNTERS

D* V1
600 sector 50Hz ADC
300Hz V1 D*
PLL V 1 EXTRACTION Ci (s)

H i(s) I
Lf
3- phase +
AC Input
Cv (s)

H v(s) Vo
+
V
ref

Fig. 5.16. Control block diagram.

163
5.6. Software Implementation

The controller software implemented in the ADSP-2101 from Analog Devices

generates the sinusoidal duty cycle functions that are synchronized with the input phase
voltages. The six-bit control word that identifies the current 600 sector that the converter
is operating in, is determined by the software program. The controller software reads in
the modulation index m, from the external feedback controller and multiplies it with the
sinusoidal duty cycles that are read from pre-stored look up tables. Duty cycle
compensation in order to compensate for the loss of duty cycle due to the ZVZCS
operation is also implemented in the program. General purpose functions such as soft-
start operation and watch-dog timer are incorporated. The details of the controller
software are presented in the following sections.

5.6.1. Synchronization with input voltages

The synchronization of the operation of the converter with the input phase
voltages is essential in the determination of the six-bit control word that contains the
present 600 sector information. Knowledge of the current 600 sector is critical in
determining the switches that are to be modulated to synthesize the reference vector. In
addition, the duty cycles that are to be read out of the look-up tables need to be
synchronized with the three phase voltages since they repeat every 600. The 600 sector
information is derived from the input phase voltages as follows:

A phase locked loop is used to derive a square wave, whose frequency is six times
the line frequency and is synchronized with the zero-cross of each of the input phase
voltages, and to feed it to the digital controller through one of the channels of the A/D
converter. The synchronization algorithm has to obtain a measure of the average duration
of 1/6th of the line frequency cycle. In other words, if the look-up table consists of N
entries, the algorithm must read the values from the table at appropriate intervals such
that the pointer to the table is at its last value or its immediate neighborhood by the end of
the current 600 sector. The algorithm must hence measure the time interval between two
successive zero-crossing instants of the synchronizing signal. The time interval thus
measured will then be used in the subsequent 600 sector to determine the spacing between
the successive values read out from the table. The synchronization algorithm
implemented in software requires the zero crossing information of one of the phase
voltages and the signal and the square wave at six times the line frequency to determine
the duty cycles and the six-bit control word.

5.7. Compensation Scheme for Standard SVM

A natural procedure to reduce phase current distortion and output voltage ripple
would be to compensate for the duty-cycle loss by pre-distorting d1. For this task a
simplified set of equations was developed (see [C22, C23] and Appendix D) and solved
for d1, i.e. compensated duty-cycle expressed in terms of desired duty-cycle dpri1 among
others. The final result is

164
 R1
p D3

Sap Sbp Scp Ds4 C1 Lf

S1 S4
Va Dap Dbp Dcp Tr + +
a Ip Ls Cb D1 If
Vb A
b Vo
Vc Vs

165
c Cpn B Co R
San Sbn Scn
D2 - -
S3 S2 n:1
Dan Dbn Dcn n Ds2 C2 CS

D4
R2

Fig.5.17. QSS-ZVZCS rectifier power stage for 208-380V line voltage, 48V output voltage,
6 kW output power and 40 kHz switching frequency
 200V/div va 200V/div

10A/div ic ,ia 10A/div

166
1V/div 1V/div
vo

5ms/div 5ms/div

a) Uncompensated b) Compensated

Fig.5.18. QSS-ZVZCS rectifier closed-loop experimental phase voltage and currents and
output voltage ripple with SVM, before and after compensation for 360V peak line voltage,
48V output voltage and 40A load current
 2 ⋅ φ sat ⋅ N sr I L  Ts ⋅ (1 − d 2 ) ⋅ (d pri 1 + d 2 ) 2 ⋅ Llk 
d pri 1 + −  − 
Vline1 ⋅ Ts N 2 ⋅ Cblk ⋅ Vline1 Ts ⋅ Vline1 
d1 = . (5.28)
I L ⋅ Ts ⋅ (Dtrf 1 + d 2 )
1−
2 ⋅ Cblk ⋅ Vline1 ⋅ N

Simulation results in Fig. 5.14(a) indicate that once the duty-cycle compensation
is incorporated second duty-cycle loss for d2 does not occur, i.e. Cases 2 and 3 in Fig.
5.12 disappear. Since (5.28) is a very involved relation that requires extra variable
sensing and big computational cost for direct implementation a power series
approximation with coefficient look-up tables is used instead. As a first cut compensation
approach, the dependence on the line voltage is only taken into account and compensated
for.

The loss of duty-cycle is mainly inversely proportional to the input line voltage
that corresponds to the first commanded duty-cycle. Moreover, this voltage is a cosine
signal from 0 to 600. The inverse relationship between the duty-cycle loss and the line
voltage results in the duty-cycle compensation to be an appropriately scaled secant
function from 0 to 600. Since the loss of duty cycle is dependent on the filter inductor
current in addition to the input voltage, a power series of the angle into the sector is
implemented in the software.

Figure 5.14(b) shows experimental waveforms for new duty-cycles, phase

voltage and compensation function. The latter exhibits a discontinuity at the sixty-degree
sector border, which invariably creates problems over wide operating ranges. Power-
series coefficients for the compensation can be tuned to reduce the effects of that
discontinuity in a narrow operating range without incurring excessive computational and
storage costs. Fig. 5.15(b) shows open-loop experimental phase currents and output
voltage ripple waveforms for the QSS-ZVZCS rectifier with SVM and duty-cycle
compensation. The latter strongly reduces phase current distortion but only causes
moderate improvements in output voltage ripple. The major difficulties for arriving at an
optimal experimental compensation that minimizes output voltage ripple (the most
critical parameter in this application) are large changes in both first applied line voltage
(from its peak to half of it) and first desired duty-cycle (normalized values from 3 2 to
zero), and the effect of the latter: the already mentioned above large discontinuity in the
compensation itself.

Closed-loop experimental phase current and output voltage ripple waveforms

without and with duty-cycle compensation are shown in Fig. 5.17(a) and 5.17(b)
respectively. Fig. 5.16(a) clearly indicates that loop bandwidth of the single input control
strategy, which already includes optimized current and voltage loop compensators,
cannot remove much of the current distortion and voltage ripple created by duty-cycle
loss, i.e. difference between applied and effective duty-cycles. On the other hand 5.17(b)

167
 d1-desired Effective duty d2-desired 600
cycle 1
0.866
θi
00

0.5 0.22
Comp I 0.12

0.16
Comp II 0.12
200V

168
effective
duty cycle 2 va 0V
0
200V
00 30 0 60 0 0 0
0 360

a) Simulation: 60 degree sector b) Experimental: 1 line cycle

Fig.5.19. QSS-ZVZCS rectifier simulated and experimental duty-cycles and

compensation with modified (duty-cycle order swapping) SVM
 Swap Border If
If
ib N N

-If -If
ic d1-pri N N

d1’-pri
ia

169
VLine1 +VCblk VLine2 +VCblk VLine1 +VCblk
N VLine2 +VCblk N
N N
Vs

d1 d2 d0 d1’ d2’ d0

Fig.5.20. QSS-ZVZCS rectifier phase currents and secondary rectifier voltage

at swapping border (phase voltage crossing) with modified SVM
indicates that duty-cycle compensation together with the selected control can remove a
lot of current distortion and voltage ripple. Unfortunately this output voltage ripple is not
acceptable for high performance applications such those in telecommunications.

5.8. Compensation Scheme for Modified SVM

Since the main causes of output voltage ripple are:

i) Discontinuity in the compensation function at sixty-degree sector crossing due

to change in first applied duty-cycle.
ii) Simultaneous requirement of near zero effective values and relatively large
applied compensated values for first duty-cycle at the end of the sixty-degree
sector.

A simple way to avoid the latter problem is to swap the order of commanded duty-
cycles somewhere inside the sixty-degree sector. Note that selecting the duty-cycle order-
-swapping instant when both phase voltages cross each other can solve the first problem.
Selection of that swapping instant causes the same required duty-cycle compensation
value, which mainly depends on first input line voltage during a short interval of time, to
be used in the switching cycles right before and after the duty-cycle swapping. As a result
the compensation function becomes continuous. All of this can be seen in Fig. 5.19(a)
where simulated duty-cycles are shown and in Fig. 5.19(b) where experimental
compensation functions with and without swapping are displayed.

Effects of this new scheme are analyzed with the help of Fig. 5.20, which shows
simplified pulsed phase-current and secondary rectifier voltage waveforms before and
after the swapping border. Even though the two desired duty-cycles could be different
from each other when their corresponding phase voltages cross the loss of duty-cycle
seen before and after the swapping border remains constant. Since both applied line
voltages have the same value an unperturbed moving average of secondary rectifier
voltage, represented by the sum of the areas of the two trapezoids, is produced across the
swapping boundary despite the difference in individual phase contribution.

However the two corresponding phase currents will exhibit a strong perturbation
in their moving average if no duty-cycle compensation is introduced together with
swapping in duty-cycle order as Fig. 5.20 shows. Therein duty-cycle loss occurs in
phase-current b before the swapping and it ceases after the swapping whereas phase-
current c experiences the opposite change. In addition, phase-current pulse positions are
altered across the swapping border. This combined effect is illustrated by open-loop
experimental waveforms in Fig. 5.21(a).

170
 vo 1V/div

5A/div
ia
200V/div

171
va
5ms/div 5ms/div

a) Uncompensated b) Compensated

Fig.5.21. QSS-ZVZCS rectifier open-loop experimental output voltage ripple, phase

current and voltage with modified SVM, before and after compensation for 360V line
voltage, 48V output voltage and 40A load current
 1V/div
vo

5A/div
ia

172
200V/div
va

5ms/div

Fig.5.22. QSS-ZVZCS rectifier closed-loop experimental output voltage ripple, phase

current and voltage with modified SVM, after compensation for 360V line voltage,
48V output voltage and 40A load current
 The latter also shows that large output voltage ripple appears when the swapping
takes place at very dissimilar phase voltage values. It should be noticed that even with an
excellent compensation function value moving averages of corresponding phase currents
experience a slight perturbation across the swap border due to alteration in current pulse
position as can be observed in the open-loop experimental waveforms shown in Fig.
5.21(b).

Closed-loop experimental phase current and output voltage ripple are shown in
Fig. 5.22. The big reduction in output voltage ripple is clear and better than that in
Fig. 5.18(b) for standard SVM with compensation. However the trade-off in phase
current distortion is noticeable when looking at Figs. 5.22 and 5.18(b).

5.9. Compatibility of Modified SVM and Compensation Scheme with Single

Input Control Strategy

The control block diagram of Fig. 5.16 indicates PLL synchronization and analog
circuitry implementation of output voltage and filter inductor current regulators together
with single input control to minimize number of sampled state variables (analog to digital
conversions) and hence to reduce implementation costs as well as program execution
time.

Experimental output voltage and phase current waveforms during transient

responses to step changes in resistive load are shown in Fig. 5.22 and 5.23. These
waveforms exhibit low distortion after the fast transient interval time, which verifies
compatibility of both new modified SVM and duty-cycle compensation with the single
input control strategy. These transient results show that the current loop has settling time
lower than three milliseconds whereas the voltage loop presents a settling time around six
milliseconds.

173
 str
10V/div
vo

ia
10A/div

174
va 200V/div

5ms/div 5ms/div

Fig.5.23. QSS-ZVZCS rectifier closed-loop response to step load disturbance (1.6 Ohm
load switched in) with swapping and compensated duty cycles for 380V peak line
voltage, 48V output voltage and 1.1 Ohm initial load
 str

vo 10V/div

175
ia 10A/div

va 200V/div

5ms/div 5ms/div

Fig.5.24. QSS-ZVZCS rectifier closed-loop response to step load disturbance (1.0 Ohm
load switched in) with swapping and compensated duty cycles for 380V peak line
voltage, 48V output voltage and 1.1 Ohm initial load
6. CONCLUSIONS

This dissertation presents a new systematic procedure to develop circuit oriented,

continuous, large signal, average models for PWM converters and some applications of
these models.

The modeling procedure is introduced in Chapter 2 and initially applied to the

open loop buck converter to illustrate its usage in both CCM and DCM operation.
Modifications of model equations to include close loop constraints are then discussed,
which allow utilization of most of the open loop model.

The primary goals of this procedure are: a) to obtain input-output structured

models that represent input and output impedance and /or loading characteristics as well
as transfer characteristics, b) to produce circuit oriented models that provide physical
insight and that can be easily used with circuit simulators and hence that take advantage
of the tools available in those simulators to perform a complete analysis within the same
simulation environment; c) to provide enough modeling versatility to include as much
internal description of the converter as needed as well as to allow for detail and accuracy
adjustments in the constraint equations according to the type and level of analysis.
Despite the emphasis on averaged circuit models simple application of Kirchoff’s laws to
these models provides a set of equations that can be used with any mathematical
simulator for ordinary differential equation.

In Chapter 3 the new procedure is applied to the well-known ZVS-FB PWM

converter. It is shown that low order Taylor’s series approximation of the constraint
equations are enough to produce a large-signal average model that smoothly transitions
between CCM and DCM operation and that very closely matches the moving average of
the state-variables from the switching model. These characteristics were not seen in
previous models for this converter. In addition a small-signal model is derived through
linearization of the large signal counterpart and it correctly represents the intrinsic
negative feedback effects extensively discussed in the literature.

176
 The only reported average model for the saturable reactor based ZVZCS-FB
PWM converter was also derived through the new procedure and it is presented in
Chapter 4. The average model exhibits excellent matching of the dynamics shown by the
moving average of switching-model state-variables, i.e. pole frequency and damping
factor, for various set of components values that lead to different types of transient
responses, i.e. under, critically and over-damped. This excellent matching is achieved by
the simple and accurate heuristic approach of modeling the effects caused by an energy
holding element through a dynamic constraint, which is also a new result. The physical
insight provide by the model clearly explains the interaction between the saturable reactor
and the blocking capacitor, i.e. the energy holding component, that creates the positive
feedback effects solely seen in this ZVZCS-FB converter and that were first reported
together with the model.

Versatility and usefulness of the new modeling procedure are shown in Chapter 5
by applying it to a QSS, soft-switched three-phase buck rectifier based on the ZVZCS-FB
converter in the previous chapter. This average model, the only one reported for this
rectifier, revealed the cause of nonlinear transfer characteristics, i.e. applied duty-cycles
to output-variables relationship, for standard SVM operation, that induced strong
distortion both in average input phase currents and average rectifier output voltage. This
variable distortion prevented usage of this rectifier, with standard SVM operation, in the
intended telecommunications applications since the feedback loop is not able by itself to
counteract those nonlinearities. Physical insight provided by the average model lead to
the development of a combined feedforward duty-cycle compensation and modified SVM
scheme that very effectively and reliably reduces distortion both in input phase currents
and output voltage. Moreover the new scheme is fully compatible with the inexpensive
but simple and effective single loop control needed in this commercial application.
Circuit simulations and experimental results verified model predictions for this rectifier
with and without duty cycle compensation for SVM and the new modified SVM and for
open loop and closed loop operation. All the experimental and analytical results
presented in this work for the QSS three-phase buck rectifier are new findings.

177
7. REFERENCES

Sorted by first author’s last name.

A
A1- D. Adar and S. Ben_Yaakov, “Generic Average Modeling and Simulation of
Discrete Controllers”, Proc. IEEE APEC, pp. 535-541, 2001.

A2- A.V. Anunciada, M.M. Silva, “On the Stability and Subharmonic Susceptibility
of Current-Mode Controlled Converters,” Proc. IEEE PESC, pp. 345-353, 1992.

A-3 P. Athalye, D. Maksimovic and R. Erickson, “Averaged Switch Modeling of

Active-Clamped Converters,” Proc. IEEE IECON, pp. 1078-1083, 2001.

B
B1- J. Baek, et. al., “Novel Zero-Voltage, Zero-Current Switching (ZVZCS) Full
Bridge PWM Converter with Low Output Current Ripple, Proc. INTELEC 1997.

B2- S. Banerjee and G. Verghese, “Nonlinear Phenomena in Power Electronics:

Bifurcation, Chaos, Control and Applications,” IEEE, 2001.

B3- R. Bass, Large Signal Tools for Power Electronics: State-Space Analysis and
Averaging Theory, Ph.D. Dissertation, University of Illinois at Urbana-Champaign,
1990.

B4- R. Bass and J. Sun, “Using Symbolic Computation for Power Electronics,” IEEE
Computer Applications in Power, pp. I-IV, 1998.

B5- R. Bass and J. Sun, “Large Signal Averaging Methods under Large Ripple
Conditions,” Proc. IEEE PESC, pp. 630-632, 1998.

B6- D. Bedrosian and J. Vlach, “ Time-Domain analysis of Networks with Internally

Controlled Switches,” IEEE Transac. on Circuits and Systems-I, vol39, no. 3, pp. 199-
212, March 1992.

B7- D. Bedrosian and J. Vlach, “An Accelerated Steady-State Method for Networks
with Internally Controlled Switches,” IEEE Transac. On Circuits and Systems-I, vol39,
no. 7, pp. 520-528, July 1992.

B8- S. Ben-Yaakov and Z. Gaaton, “A Unified Model of Current Feedback in Switch

Mode Converters,” Proc. IEEE ISCAS’92, pp. 1891-1894, May 1992.

178
B9- S. Ben-Yaakov, S. Glozman and R. Rabinovici, “Envelope Simulation by Spice-
Compatible Models of Electric Circuits Driven by Modulated Signals,” IEEE Transac. on
Industrial Electronics, vol 47, no. 1, pp. 222-225, February, 2000.

B10- A. Brambilla and P. Maffezzoni, “Envelope following Method for the Transient
Analysis of Electrical Circuits,” IEEE Transac. On Circuits and Systems-I, vol 47, no. 7,
July 2000.

B11- A. Brown, R. Middlebook and S. Cuk, “A General Unified Approach to Modeling

Switching Converter Power Stages,” Proc. IEEE PESC, pp. 18-34, 1976.

B12- J. Burdio and A. Martinez, “A Unified Discrete-Time State-Space Model for

Switching Converters,” IEEE Transac. on Power Electronics, vol 10, no. 6, pp. 694-707,
February, 2000.

C
C1- V. Caliskan, G. verghese and A. Stankovic, “Multifrequency Averaging of
DC/DC converters,” IEEE Transac. on Power Electronics, vol 14, no. 1, pp. 124-133,
1999.

C2- F. Canales, P. Barbosa and F. Lee, “A Zero Voltage and Zero Current Switching
Three-Level DC/DC Converter,” Proc. IEEE APEC, pp. 314-320, 2000.

C3- K. Chakrabarty, G. Poddar and S. Banerjee, “Bifurcation Behavior of Buck

Converter,” IEEE Transac. on Power Electronics, vol 11, no. 3, pp. 439-447, 1996.

C4- C. Chan and K. T. Chau, “Nonlinear Modeling of Pulsewidth-Modulated and

Quasi-Resonanat Converters,” IEEE. Proceeding of PE&MC, pp. 229-234, 1992.

C5- J. Chen, R. Erickson and D. Maksimovic, “ Averaged Switch Modeling of

Boundary Conduction Mode Dc to Dc Converrters,” Proc. IECON, pp. 844-849, 2001.

C6- J. Chen and K. Ngo, “ Simplified Analysis of PWM Converters Operating in

Discontinuous Mode Using Alternate Forms of the PWM Switch Models,” Proc. IEEE
Southeastcom, pp. 505-509, 2000.

C7- J. Chen and F. Rodriguez, “Duo-Mode Non-Linear State-Space Model of a

Current Mode Buck Converter,” Proc. IEEE APEC, pp. 53-58, 1988.

C8- J. Cheng and A. Witulski, “Steady-State and Large-Signal Design of Current-

Programmed DC-DC copverters,” IEEE Transac. on Power Electronics, vol 12, no. 4, pp.
743-751, July 1997.

179
C9- J. Cho, J. Rim and F.C. Lee, “Zero-Voltage and Zero-Current Switching Full-
Bridge PWM Converter Using Secondary Active Clamp,” Proc. IEEE PESC, 1996.

C10- J. Cho, [Link]., “Novel Zero-Voltage Zero-Current Switching (ZVZCS) Full-Bridge

PWM Converter Using a Simple Auxiliary Circuit,” Proc. IEEE APEC, pp. 834-839,
1998.

C11- J. Cho [Link]., Zero-Voltage and Zero-Current Switching Full-Bridge PWM

Converter for High Power Applications, Proc. IEEE PESC, pp. 95-101, 1994.

C12- B. Cho, et al., “A Novel Secondary Clamping Circuit Topology for Soft-
Switching Full-Bbridge PWM DC-DC Converter, ,” Proc. IEEE APEC, pp. 840-845,
1998.

C13- B. Choi [Link]., “Control Strategy for Multimodule Parallel Converter System,”
Proc. IEEE PESC, pp. 225-234, 1990.

C14- J. Choi, [Link]., “Empirical Data Modeling of Power Converters,” Proc. IEEE
PESC, pp.1648-54, 1996.

C15- H. Choi, et. al., “Modeling, analysis and Design of 10kW Parallel Module Zero-
Voltage Zero-Current Switched Full-Bridge PWM Convererter,” Proc. IEEE APEC, pp.
321-326, 2000.

C16- H. Choi, et. al., “ Analysis and Design Consideration of Zero-Voltage and Zero
Current-Switching (ZVZCS) Full-Bridge PWM Converters,” Proc. IEEE PESC, pp.1835-
1840, 2002.

C17- H. Chung and A. Ionovici, “Large-Signal Stability of PWM Switching

Regulators,” Proc. IEEE PESC, pp. 1123-1126, 1995.

C18- H. Chung, A. Ionovici and J. Zhang, “Describing Functions of Power Electronics

Circuits Using Progressive Analysis of Circuit Waveforms,” IEEE Transac. on Circuit
and Systems-I, vol. 47, no. 7, pp. 1026-1037, July 2000.

C19- P. Cooke, “Modeling Average Current Mode Control,” Proc. IEEE APEC, pp.
256-262, 2000.

C20- C. Cuadros, [Link]., “Design Procedure and Modeling of High Power High
Performance Zero-Voltage Zero-Current Switched, Full-Bridge PWM Converter,” Proc.
IEEE APEC, pp. 790-798, 1997.

180
C21- C. Cuadros and D. Boroyevich, “Accurate Large Signal Modeling of Zero-
Voltage Zero-Current Switched, Full-Bridge PWM Converter,” Proceedings of the Fifth
European Space Power Conference, pp. 119-124, 1998.

C22- C. Cuadros, et. al. “Modeling, Control and Implementation of the Quasi-Single
Stage Three-Phase Zero-Voltage Zero-Current Switched Buck Rectifier,” Proc. IEEE
APEC, pp. 248-254, 1999.

C23- C. Cuadros, et. al. “Modeling and Comparison of Two Modified Vector
Modulation Schemes with Feed-Forward, for the Quasi-Single Stage Three-Phase Zero-
Voltage Zero-Current Switched Buck Rectifier,” Proceedings of EPE’99, 1999.

C24- D. Czarkowski and M. Kazimierczuk, “Spice Compatible Averaged Models of

PWM Full-Bridge DC-DC \Converters,” IEEE. Proceeding of PE&MC, pp. 488-493,
1992.

D
D1- J. Deane and P. Hamill, “Instability, Subharmonics and Chaos in Power
Electronics Circuits,” IEEE Transac. on Power Electronics, vol 5, no. 3, pp. 260-268,
1990.

D2- C. Deml and P. Turkes, “ Fast Simulation Technique for Power Electronic circuits
with Widely Different Time Constants,” IEEE Transac. on Industry Applicatios, vol 35,
no. 3, pp. 657-662, May/June, 2000.

E
E1- M. Elbuluk, G. VErghese and J. Kassakian, “Sampled-Data Modeling Control of
Resonant Converters,” IEEE Transac. on Power Electronics, vol 3, no. 3, pp. 344-354,
1988.

E2- S. Eng, R. Oruganti and Y. Liang, “An Automated Algorithm for Small Signal
Analysis of DC-DC Power Converters,” IEEE Transac. on Power Electronics, vol 11, no.
1, pp. 132-141, January 1996.

E3- R. Erickson, S. Cuk and R. Middlebrook, “Large Signal Modeling and Analysis
of Switching Regulators,” Proc. IEEE PESC, pp. 240-250, 1982.

E4- R. Erickson, “Advances in Averaged Switch Modeling,” Seminar at IEEE PESC,

1999.

181
E5- R. Erickson and D. Maksimovic, “Fundamental of Power Electronics,” Kluwer
Academics, 2001

F
F1- C. Fang, “Sampled-Data Analysis and Control of DC-DC Switching Converters,
Ph.D. Thesis, University of Maryland, 1997.

F2- N. Femia and V. Tucci, “On the Modeling of PWM Converters for Large Signal
Analysis in Discontinuous Conduction Mode,” IEEE Transac. on Industrial Electronics,
vol 9, no. 5, 487-496, February, 2000.

F3- N. Femia, G. Spagnuolo and V. Tucci, “State-space Models and Order Reduction
for switching Converters in Discontinuous Modes,” IEEE Transac. On Power
Electronics, vol. 10, no. 6, pp. 640-650, Jan 1995.

F4- E. Fossas and G. Olivar, “Study of Chaos in the Buck Converter,” ,” IEEE
Transac. On Circuit and Syatems-I, Vol. 43, No. 1, pp. 13-25, January 1996.

G
G1- L Garcia de Vicuna, [Link]., Computer-Aided Discrete-Time Large–Signal Análysis
of Switching Regulators,” IEEE Trans. on Power Electronics, vol. 7, no. 1, pp.75-82,
1992.

G2- J. Glasert and A. Witulski, “Output Plane Analysis of Load Shaping in Multiple
Module Converter Systems, IEEE Trans. on Power Electronics vol. 9, no. 1, 1994.

G3- F. Guinjoan, [Link]., Large-Signal Modeling and Simulation of Switching DC-DC

Converters,” IEEE Trans. on Power Electronics, vol. 12, no. 3, pp.485-494, 1997.

G4- R. Griffin, “Unified Power Converters Models for Continuous and Discontinuous
Mode,” Proc. IEEE PESC, pp. 853-860, 1989.

H
H1- D. Hamil, et. al., “Modeling of Chaotic DC-DC Converters by Iterated Nonlinear
Mappings,” IEEE Transac. On Power Electronics, Vol. 7, No. 1, pp. 55-61, January
1992.

182
H2- S. Hiti, “Modeling and Control of Three-Phase PWM Converters,” Ph.D. Thesis
VPI&SU, July 1995.

H3- G. Hua, “Soft-Switching Techniques for Pulse-Width Modulated Converters,”

Ph.D. thesis, VPI&SU, April 1994.

H4- F. Huliehel and [Link]-Yaakov, “Low Fequency Sampled-Data Models of Switched

Model DC-Dc Converters,” IEEE Transac. On Power Electronics, Vol. 6, No. 1, pp. 55-
61, January 1991.

H5- P. Huynh and B. Cho, “Empirical Small Signal Modeling of Switching Converters
Using Pspice,” Proc. IEEE PESC, pp.809-15, 1995.

I
I1- M. Ilic, S. Leeb and K. Liebezeit, “Exact Nonlinear Analysis of Switched Mode
Power Converters,” Proc. PESC, pp. 977-986, 1988.

J
J1- S. Jalali, et. al., “Switcing Time Bifurcation in a Thyristor Controlled Reactor,”
IEEE Transac. on Circuits and Systems-I, vol 43, no. 3, pp. 209-217, 1996.

J2- S. Jeon and G. Cho, “A Zero-Voltage and Zero Current Switching Full Bridge
DC-DC Converter with Transformer Isolation,” IEEE Transac. On Power Electronics,
Vol. 16, No. 5, pp. 55-61, Setptember 2001.

J3- S. Jeon, et. al., “A Primary-Side-Assisted Zero-Voltage and Zero-Current

Switching Three-Level DC-DC Converter with Phase-Shift Control,” IEEE Confer
Record. 2002.

J4- Y. Jiang, F.C. Lee, “Simple High Performance Three-Phase Boost Rectifier,”
Proc. IEEE PESC, pp.1158-63, 1994.

J5- H. Jin, “Behavior-Mode Simulation of Power Electronics Circuits,” IEEE

Transac. on Power Electronics, vol 12, no. 3, pp. 443-452, 1997.

K
K1- M. Kazimierczuk, “Transfer Function of Current Modulator in PWM Converters
with Current-Mode Control,” IEEE Transac. On Circuits and System-I, vol. 47, no. 9, pp.
1407-1412, September 2000.

183
K2- E. Kim, [Link]., “An Improved ZVZCS PWM Full-Bridge DC-DC Converter Using
Energy Recovery Snubber,” Proc. IEEE APEC, 1997.

K3- E. Kim, [Link]., “An Improved ZVZCS PWM FB DC/DC Converter Using the
Modified Energy Recovery Snubber,” Proc. IEEE APEC, pp.119-124, 2000.

K4- D. Kimhi and S. Ben-Yaakov, “A Spice Model for Current Mode PWM
Converters Operating Under Continuous Inductor Current Conditions,” IEEE Transac.
On Power Eelctronics, vol. 6, no. 2, pp. 281-286, April 1991.

K6- A. Kislovski, R. Redl and N. Sokal, “Dynamic Analysis of Switching-Mode DC-

DC Converters,” Van Norstrand Reinhold, New York, 1991.

K5- P. Krein, [Link]., “On the Use of Averaging for the Anlaysis of Power Electronic
Systems,” IEEE Trans. on Power Electronics, vol. 5, no. 2, pp. 182-190, 1990.

K7- P. Krein and R. Bass, “Geometric Formulation, Classifications and Methods for
Power Electronic Systems,” Proc. IEEE PESC, pp. 499-505, 1990.

K8- N. Kutkut and G. Luckjiff, “Current Mode Control of a Full-Bridge DC-to_DC

Converter with a Two Inductor Rectifier,” Proc. IEEE PESC, pp. 203-209, 1997.

L
L1- D. Lee, B. Lee and D. Hyun, “An Improved Full-Bridge Zero-Voltage Transition
PWM DC-DC Converter with Zero-Voltage, Zero-Current Switching of the Auxiliary
Switches,” Proc. IEEE APEC, pp. 816-282, 1998.

L2- F.C. Lee, [Link]., “Generalized Computer-Aided Discrete Time-Domain Modeling

and Analysis of DC-DC Converters,” IEEE Trans. on Industrial Electronics and Control
Instrumentation, vol.26, no.2, pp. 58-69, 1979.

L3- S. Leeb, J. Kirtley and G. Verghese, “Recognition of Dynamic Patterns in DC-DC

switching Converters,” Proc. IEEE PESC, pp. 26-33, 1989.
Selective Modal Analysis tools in pattern recognition algorithm.

L4- B. Lehman and R. Bass, “Extensions of Averaging Theory for Power Electronics
Systems,” IEEE Trans. on Power Electronics vol. 11, no. 4, pp.542-553, 1996.

L5- B. Lehman and R. Bass, “Switching Frequency Dependent Averaged Models for
PWM DC-DC Convereters,” IEEE Transac. on Power Electronics, vol. 11, no. 1, pp. 89-
98, 1996.

184
L6- B. Lehman and R. Bass, “Recent Advances in Averaging Theory for PWM DC-
DC Converters,” Proc Conference on Decision and Control, pp. 4467-4471, December
1996.

L7- R. Leyva, [Link]., “Identification and Control of Power Converters by Means of

Neural Networks,” IEEE Transac. on Circuits and Systems I. Fundamental Theory and
Applications, vol. 44. No. 8, pp.735-42, 1997.

L8- D. Li, R. Tymerski and T. Ninomiya, “PECS – Power Electronics Circuit

Simulator”, Proc. IEEE COMPEL, pp.159-165, 2000.

L9- B. Lin and Y. Lee, “A Unified Approach to Modeling, Synthesizing and

Analyzing Quasi- Resonant Converters,” IEEE Transac. on Power Eelctronics, vol. 12,
no. 6, pp. 983-992, November 1997.

L10- G. Lirer, A. Strollo and A. Luciano, “ A Simplified Model of Current-Controlled

Switching Converters in Discontinuous Current-Mode,” Proc. EPE, pp. 240-245, 1993.

L11- Y. Liu and P. Sen, "A General Unified Large-Signal Model for Current
Programmed DC-DC Converters,” IEEE Transac. on Power Electronics, vol. 9, no. 4, pp.
414-424, 1994.

L12- Z. Lizhi, [Link]., “A Novel Soft Switching Full-Bridge PWM DC-DC Converter
With Auxiliary Resonant Commutated Network, Proc. INTELEC 1996.

L13- Y. Lo and R. King, “Sampled-Data Modeling of the Average-Input Current-

Mode-Controlled Buck Converter,” IEEE Transac. on Power Electronics, vol 14, no. 5,
pp. 918-927, 1999.

L14- X. Luan and Y. Yang, “Improved Phase Shifted Zero-Voltage and Zero-Current
Switching PWM Converer,” APEC Proc. pp. 811-815, 1998.

L15- R. Lutz and M. Grotzbach, “Straightforward Discrete Modeling for Power

Converter Systems,” Proc. IEEE PESC, pp. 761-770, 1985.

L16- Y-S. Lee, K.C. Wong and C.K. Ng, “Behavioral Modeling of Magnetizing
Currents in Switch-Mode DC-DC Converters,” IEEE Transac. on Industrial Electronics,
vol. 47, no. 1, pp. 36-44, 2000.

L17- S. Lyshevsky, “Resonant Converters: Nonlinear Analysi and Control,” ,” IEEE

Trans. on Industrial Electronics, vol. 47, no. 4, pp. 751-758, August 20001.

185
M
M1- D. Maksimovic, et. al. “Modeling and Simulation of Power Electronic
Converter,” Proceeding of the IEEE, vol. 89, no. 6, pp. 898-912, June 2001.

M2- D. Maksimovic and S. Cuk, “A Unified Analysis of PWM Converters in

Discontinuous Modes,” IEEE Trans. on Power Electronics, vol. 6, no. 3, pp. 476-490,
1991.

M3- H. Mao, et al., “Three Phase AC-DC Power Converter Final Report to
Kollmorgen,” Virginia Power Electronics Center, VPI&SU, August 1997.

M4- P. Maranesi, “Small-Signal Circuit Modeling in the Frequency Domain by

Computer_Aided Time-Domain Simulation,” IEEE Trans. on Power Electronics, vol. 7,
no. 1, pp. 83-88, 1992.

M5- E. Mayer and R. King, “An Improved Sampled-Data Current-Mode Control

Model which Explains the Effects of Control Delay,” IEEE Transac. On Power
Electronics, Vol. 16, No. 3, pp. 369-374, May 2001.

M6- S. Miaosen, K. Wanying and Q. Zhaoming, “A Novel Average Model for a Single
Stage PFC Converter,” Proc. IEEE COMPEL, pp. 151-156, 2000.

M7- N. Mohan, T. Undeland and P. Robbins, “Power Electronics Converters,

Applications and Design,” Wiley, New York, 1995.

N
N1- M. Nakano, Y. Iijima and T. Chin, “Quasi-State Variable Method for Precise
Modeling of DC-DC Converter Circuits”, Proc. IEEE IECON, pp. 1331-1335, 1993.

N2- K. Ngo, Topology and Analysis in PWM Inversion, Rectification and

Cycloconversion, Ph.D. Dissertation, California Institute of Technology, Pasadena, CA,
1984.

N3- T. Ninomiya, et al, “A Unified Analysis of Resonant Converters,” IEEE Transac.

on Power Electronics, vol 6, no. 2 ,, pp. 260-70, 1991.

N4- G. Nirgude, R. Tirumala and N. Mohan, “A New Large-Signal Average Model

for single-Switch DC-DC Converters Operating in both CCM and DCM,” Proc. IEEE
PESC, pp. 1736-1741, 2001.

186
O
O1- O. Ojo and V. Madhani, “Time-Averaging Equivalent Circuit Analysis and
Controllers Design of Full-Bridge Parallel Resonant DC/DC Converter,” Proc. IAS, pp.
977-989, 1991.

O2- J. Oliver, et. al., “Systematic Approach for Developing Large-Signal Averaged
Models for Multi-Output PWM Converters,” Proc. IEEE PESC, pp. 696-701, 2000.

O3- R. Oruganti and F.C. Lee, “Resonant Processors Part I: Sate Pane Alysis,” IEE
Tansac. on Idustry Aplications, vol. 21, no. 6, pp.1461-71, 1985.

O4- R. Oruganti and Y. Liang, “An Automated Algorithm for Small Signal Analysis
of DC-DC Power Converters,” IEEE Transac. on Power Electronics, vol 11, no. 1, , pp.
13-18, 1996.

P
P1- S. Pavljasevic and D. Maksimovic, “Using a Discrete-Time Model for Large-
signal Analysis of a Current-Programmed Boost Converter,” Proc. IEEE PESC, pp. 715-
721, 1991.

P2- P. Pejovic and D. Maksimovic, “A New Algorithm for Simulation of Power

Electronic Systems Using Piece-Wise Linear Device Models,” IEEE Transac. On Power
Electronics, Vol. 10, No. 3, pp. 340-348, May 1995.
NEW PROGRAM, DIFFERENT DOMAIN

P3- D. Perreault and G. Verghese, “Time Varying Effects and Averaging Issues in
Models for Current-Mode Control,” IEEE Transac. On Power Electronics, Vol. 12, No.
3, pp. 453-461, May 1997.

P4- C. Piccard, “Bifurcations of Limit Cycles in Periodically Forced Nonlinear

Systems: The Harmonic Balance Method, IEEE Trans. on Circuits and Systems I.
Fundamental Theory and Applications, vol. 41, no. 4, pp315-320, 1994.

P5- A. Pietkiewicz and D. Tollik, “Unified Topological Modeling Method of

Switching DC-DC Converters in Duty Ratio Programmed Mode,” ,” IEEE Transac. On
Power Electronics, Vol. PE-2, No. 3, pp. 218-226, July 1987.

R
R1- Y. Ren, et. al., “A novel Average Model for Single Switch DC-DC Converter,”
Proc. IEEE PIEMC, pp. 436-439, Record 2000.

187
R2- C. Ri and G. Cho, “Phasor Transformation and its Application to the DC/AC
Analysis of Frequency Phase Controlled Series Resonant converters (SRC),” ,” IEEE
Transac. On Power Eelctronics, Vol. 5, No. 2, pp. 201-211, April 1990.

R3- R. Ridley, “Small Signal Analysis of Parallel Power Converters, [Link]. Thesis,
VPI&SU, March 1986.

R4- R. Ridley, “A New Continuos-Time Model for Current Mode Control”, IEEE
Trans. on Power Electronics, vol. 6, pp. 271-280, 1991.

R5- D. Rodriguez and J. Chen, “A Refined Nonlinear Averaged Model for Constant
Frequency Current Mode Controlled PWM Converters,” IEEE Trans. on Power
Electronics, vol. 6, no. 4, pp. 656-664, 1991.

S
S1- J. Sabate, [Link]., “Design Considerations for High Voltage High Power, Full-
Bridge Zero-Voltage Switched PWM Converter,” Proc. IEEE APEC, pp. 275-84, 1990.

S2- S. Sanders, [Link]., Generalized Average Method for Power Conversion Circuits,”
IEEE Trans. on Power Electronics, vol. 6, no. 2, pp. 521-259, 1991.

S3- S. Sanders, “On Limit Cycles and the Describing function Method in Periodically
Switched Circuits,” IEEE Transac. on Circuits and systems-I, vol. 40, no. 9, pp. 564-572,
September 1993.

S4- S. Sanders and G. Verghese, “Synthesis of Averaged Circuit Models for Switched
Power Converters,” IEEE Transac. on Circuits and Systems, vol 38, no. 8, pp. 905-15,
1991.

S5- T. Sato, “A Novel Switching Converter Simulation Algorithm by Averaged State

Transition Matrices,” Proc. IEEE INTELEC, pp. 329-332, 1998.

S6- M. Shen and Z. Qian, “A Unified Average Model for Single Stage and Two Stage
Power Factor Correction Converters,” Proc. IEEE APEC, pp. 125-129, 2001.

S7- S. Singer, “Gyrators Application in Power Processing Circuits,” IEEE Transac.

on Power Electronics, vol. 34, no.3, pp.313-18, 1987.

S8- S. Singer and R. Erickson, “Canonical Modeling of Power Processing Circuits

Based on the POPI Concept,” IEEE Transac. on Power Electronics, vol. 7, no. 1, pp. 37-
42, 1992.

188
S9- H. Sira-Ramirez, “A Geometric Approach to Pulse-Width-Modulated Control in
Nonlinear Dynamical Systems,” IEEE Transac. On Automatic Control, vol AC-34, no. 2,
pp 184-187, Feb 1989.

S10- K. Siri, I. Batarseh and C. Lee, “Frequency Response for the Conventional
Parallel Resonant Converter Based on the State-Plane Diagram,” IEEE Transac. on
Circuits and Systems, vol 40, no. 1, pp. 33-42, January 1993.

S11- K. Smedley and S. Cuk, “Switching Flow-Graph Nonlinear Modeling

Technique,” ”, IEEE Transac. On Power Eelctronics, Vol. 9, No. 4, pp. 405-413, July
2004.

S12- J. Sun and H. Grotstollen, “Symbolic Analysis Methods for Average Modeling of
Switching Power Converters,” IEEE Transac. on Power Electronics, vol. 12, no. 3,
pp.537-46, 1997.

S13- J. Sun and Grotstollen, “Averaged Modelling of Switching Power Converters:

Reformulation and Theoretical Basis,” Proc. IEEE PESC, pp. 1165-72, 1992.

S14- J. Sun and Grotstollen, “Averaged Modelling and Analysis of Resonant

Converters,” Proc. IEEE PESC, pp. 707-13, 1993.

S15- J. Sun and R. Bass, “A New Approach to Avergaed Modeling of PWM

Converters with Current-Mode Control,” Proc. IEEE IECON, pp. 599-604, 1997.
KBM method for ripple calculation PWM only.

S16- J. Sun [Link]., “Averged Modeling of PWM Converteres Operation in

Discontinuous Conduction Mode”, IEEE Transac. On Power Eelctronics, Vol. 16, No. 4,
pp. 482-492, May 2001.

S17- J. Sun, B. Heck and B. Lehman, “Continuous Approximation and the Stability of
Avergaing,” Proc. IEEE COMPEL, pp. 139-144, 2000.

S18- C. Sun, B. Lehman and R. Ciprian, “Dynamic Modeling and Control in Average
Current Mode Controlled PWM DC/DC Converters,” Proc. IEEE PESC, pp. 1152-1157,
1999.

S19- J. Sun and R. Bass, “Practical Design Issues for Average Current Control,” Proc.
IEEE APEC, pp. 980-986, 1999.

S20- J. Sun, “Unified Averaged Switch Models for Stability analysis of Large
Distributed Power Systems,” Proc. IEEE APEC, pp. 249-255, 2000.

189
S21- J. Sun, et. al., “Modeling of PWM Converters in Discontinuous Conduction Mode
– A Reexamination,” Proc. IEEE PESC, pp. 615-622, 1998.

S22- J. Sun, X. X. Wang and X. Han, “Averaged Modeling and Analysis of Buck ZCS-
QRC”, Proc. IEEE ISIE, pp. 680-684, 1992.

S23- T. Suntio, [Link]., Dynamic Effects of Inductor Current Ripple in Peak-Current and
Average-Current Mode Control,” Proc. IEEE IECON, pp. 1072-1077, 2001.

S23- T. Suntio, “Analysis and Modeling of Peak-Current Mode-Controlled Buck

Converter in DICM,” IEEE Trans. on Industrial Electronics, vol. 48, no. 1, pp. 127-135,
2001.

T
T1- F. D. Tan and R. D. Middlebrok, “A Unified Model for Current Programmed
Converters,” IEEE Transac. On Power Electronics, Vol. 10, No. 4, pp. 397-408, July
1995.

T2- V. Thottuvelil, D. Chin and G. Verghese, “Hierarchical Approaches to Modeling

High-Power-Factor AC-DC Converters,” IEEE Transac. On Power Electronics, Vol. 6,
No. 2, pp. 179-187, July 1991.

T3- C.K. Tse, “Flip Bifurcation and Chaos in Three-State Boost Switching
Regulators,” IEEE Trans. on Circuits and Systems, vol. 41, no. 1, pp. 16-23, 1994.

T4- F. Tsai, “Small-Signal and Transient Analysis of a Zero-Voltage Switched, Phase

Controlled PWM Converter Using Averaged Switch Model,” IEEE Trans. on Industrial
Applications, vol. 29, no. 3, pp. 493-499, May/June 1993.

T5- R. Tymerski and D. Li, “State Space Models for Current Programmed Pulse-
Width-Modulated Converters,” IEEE Trans. on Power Electronics, vol. 8, no. 3, pp. 271-
278, 1993.

T6- R. Tymerski, “Applications of the Time Varying Transfer Function for Exact
Small-Signal Analysis,” Proc. IEEE PESC, pp. 716-732, 1997.

T7- R. Tymerski, “Sampled Data Modeling of Switched Circuits, Revisited,” Proc.

IEEE PESC, pp. 395-401, 1993.

T8- R. Tymerski and V. Vorperian, “Generalization, Classification and Analysis of

Switched Mode DC-DC Converters by the Use of Converter Cells,” Proc. IEEE
International Telecommunication Energy, pp. 181-196, 1986.

190
T9- R. Tymerski, “Frequency Analysis of Time-Interval-Modulated Switched
Networks,” IEEE Transac. On Power Electronics, Vol. 6, No. 2, pp. 287-295, July 1991.

V
V1- E. van Dijk, [Link]., “PWM-Switch Modeling of DC-DC Converters,” Transac. on
Power Electronics, vol. 10, no. 6, pp.659-665, 1995.

V2- H. van der Broeck, H. Skudelny and G. Stanke, “Analysis and Realization of a
Pulse Width Modulator on voltage Space Vectors,” Proc. IEEE IAS, pp. 244-251, 1986.

V3- G. Verghese, C. Bruzos and K. Mahabir, “Average and Sampled-Data Models for
Current Mode Control, A Reexamination,” Proc. IEEE PESC, pp. 484-491, 1989.

V4- G. Verghese, M. Elbuluk and J. Kassakian, “A General Approach to Sampled-

Data Modeling for Power Electronic Circuits,” IEEE Transac. On Power Electronics,
PE-1, no. 2, pp. 76-89, April 1986.

V5- V. Vlatkovic, [Link]., “Small-Signal Analysis of the Zero-Voltage Switched, Full-

Bridge PWM Converter,” Proc. IEEE HFPC, pp. 262-72, 1990.

V6- V. Vlatkovich, D. Boroyevich and F.C. Lee, A Zero-Voltge Switched Three-

Phase Isolated PWM Buck Rectifier,” IEEE Transac. on Power Electronics, vol 10, no.
2, pp. 148-57, 1995.

V7- V. Vlatkovitch, “Three Phase Power Conversion Using Soft-Switching PWM

Techniques,” Ph.D. thesis, VPI&SU, October 1994

V8- V. Vorperian, “Simplified Analysis of PWM Converters Using the PWM Switch,
Parts I & II, Continuos and Discontinuous Conduction Mode,” Proc. VPEC Seminar, pp.
1-20, 1989.

V9- V. Vorperian, R. Tymerski and F.C. Lee, “Equivalent Circuit Models for
Resonant and PWM Switches, IEEE Trans. on Power Electronics, vol. 4, no. 2, pp205-
214, 1989.

V10- V. Vorperian, “Analysis of Current Mode Controlled PWM Converters Using the
Model of the Current Controlled PWM-Switch,” Proc. PCIM, 1990.

V11- V. Vorperian, “Approximate Small-signal Analysis of the Series and the Parallel
Resonant Converter,” IEEE Transac. On Power Electronics, vol. 4, no. 1, pp. 15-24, Jan
1989.

191
W1- K. Wang [Link]., “Novel DC-Rail Soft Switched Three-Phase Voltage Source
Inverters,” Proc. IEEE IAS annual meeting, pp. 2610-17, 1995.

W2- [Link], [Link]., “A New Quasi-Single Stage Isolated Three-Phase ZVZCS Buck
Rectifier,” Proc. IEEE PESC, pp. 449-55, 1996.

W3- A. Witulski and R. Erickson, “Extension of State-Space Averaging to Resonant

Switches - and Beyond ,” Proc. IEEE PESC, pp. 476-483, 1989.

W4- A. Witulski, A. Hernandez and R. Erickson, “Small Signal Equivalent Circuit

Modeling of Resonant Converters,” IEEE Transac. On Power Electronics, vol. 6, no. 3,
pp. 11-27, Jan 1991.

W5- K.H. Wong and S. Chung, “A Systematic Technique for Small-Signal Low-
Frequency Characterization of PWM DC/DC Converters,” IEEE Transac. On Industrial
Electronics, vol. 47, no. 1, pp. 45-54, February 2000.
W6- X. Wu, [Link]., “High Power High Frequency Zero-Current Transition Full-Bridge
DC-DC Converter,” Proc. IEEE APEC, pp. 823-828, 1998.

W7- T. Wu and Y. Chen, “Modeling PWM DC/DC Converters Out of Basic Converter
Units,” IEEE Transac. On Power Electronics, vol. 13, no. 5, pp. 870-881, September
1998.

X
X1- C. Xiao, B. Lehman and J. Sun, “Ripple Effects on Small-signal Models in
Average Current Mode Control,” Proc. IEEE APEC, pp. 818-823, 2000.

X2- J. Xie, B. Lehman and H. Xu, “In-Place Averaged switch Models that Include
Commutation Dynamics,” Proc. IEEE COMPEL, pp. 145-150, 2000

X3- J. Xu and C. Lee, “Generalized State-Space Averaging Approach for a Class of

Periodically Switched Networks,” IEEE Transac. On Circuits and systems-I, vol 44, no.
11, pp. 1078-1081, Nov 1997.

X4- J. Xu and J. Yu, “Time Averaging Equivalent Circuit Analysis of Switching DC-
DC Converters in Discontinuous Conduction Mode,” Proc. IEEE IECON, pp. 656-660,
1988.

X5- X. Xu, “Small-Signal Model for Current Mode Control Full-Bridge Phase-Shifted
ZVS Converter,” Proc. IEEE PIEMC, pp. 514-518, 1993.

192
Y
Y1- E. Yang, “Extended Describing Function Method for Small-Signal Modeling of
Resonant and Multiresonant Converters,” Ph.D. thesis, VPI&SU, February 1994.

Y2- J. Yu and J. Xu, “Time Averaging Equivalent Circuit Analysis for a Class of
Periodically Switching Linear Network,” Proc. IEEE ISCAS, pp. 1139-1142, 1988.

193
A Saber Template and Schematics for Buck Converter

A1. Listing of Saber Template for Buck Converter Average Model

element template buck_duo_1 com ilf vout vin d1 d2 i_equiv v_equiv zeros =
Ts,Lf

electrical com, ilf, vout, vin, d1, d2, i_equiv, v_equiv, zeros

number Ts, Lf

{
val v delta_ilf, ipk, d_off, vilf, vvout, vvin, vd1, vd2,
v_vequiv, v_iequiv, v_zeros, vdeltaup, vdeltadwn

var i i_iequi, i_vequi, i_zeros

values {
vilf = v(ilf)-v(com)
vvout = v(vout)-v(com)
vvin = v(vin)-v(com)
vd1 = v(d1)-v(com)
vd2 = v(d2)-v(com)
d_off = 1 - vd1
vdeltaup = vd1*(vvin-vvout)*Ts/Lf
vdeltadwn = vvout*d_off*Ts/Lf

delta_ilf = (vdeltaup*vd1 + vdeltadwn*d_off)/2

if (vilf - delta_ilf > 0 ) {

ipk = vilf + delta_ilf
}
else {
if ( vdeltaup - vdeltadwn > 0 ) {
ipk = vilf + delta_ilf
}
else {
ipk = 2*vilf/(vd1+vd2+1e-7)
}
}

v_vequiv = vvin*vd1/(vd1+vd2+1e-7)
v_iequiv = vilf*vd1/(vd1+vd2+1e-7)
v_zeros = Ts*vd2*vvout - ipk*Lf

} # end of values section

equations {

i(zeros->com) += i_zeros
i_zeros : v(zeros) - v(com) = v_zeros

i(i_equiv->com) += i_iequi

194
 i_iequi : v(i_equiv) - v(com) = v_iequiv

i(v_equiv->com) += i_vequi
i_vequi : v(v_equiv) - v(com) = v_vequiv

} # end of equations section

} # end of template body

195
196
Fig.A.1. Saber schematics for Buck converter
B Listing of Saber templates for ZVS-FB PWM Converter
Average Models

B1. Previous Model

element template zvs_duo_PREVIOUS com ilf vout vin Don Dtrf

D2 i_equiv v_equiv i_deviat zero_Dtrf zero_D2 = Ts, Lf,
Llk, N

electrical com, ilf, vout, vin, Don, Dtrf, D2, i_equiv,

v_equiv, i_deviat, zero_Dtrf, zero_D2

number Ts, Lf, Llk, N

{
val v delta_ilf, ipk, d_off, vilf, vvout, vvin, vDon,
vDtrf, vDoff, VDch, vD2,
v_vequiv, v_iequiv, v_ideviat, v_zero_D2,
v_zero_Dtrf, vdeltaup, vdeltadwn, Lequiv, NTS
var i i_iequi, i_vequi, i_ideviat, i_zero_D2, i_zero_Dtrf

values {

vilf = v(ilf)-v(com)
vvout = v(vout)-v(com)
vvin = v(vin)-v(com)
vDon = v(Don)-v(com)
vDtrf = v(Dtrf)-v(com)
vD2 = v(D2)-v(com)
Lequiv = Lf + Llk/N**2
vDoff = 1 - vDtrf
NTS = N*Ts
vdeltaup = vDtrf*(vvin/N-vvout)*Ts/Lequiv
delta_ilf = vdeltaup/2

if (vilf - delta_ilf/2 > 0 ) {

ipk = vilf + delta_ilf

197
 vDch = (Vilf)*2*Llk/vvin/NTS
}
else {

ipk = 2*vilf/(vDtrf+vD2+1e-7)
vDch = 0
}
v_ideviat = vDch*(vilf)
v_vequiv = vvin*vDtrf/(vDtrf+vD2+1e-7)/N
v_iequiv = vilf*vDtrf/(vDtrf+vD2+1e-7)/N
v_zero_D2 = Ts*vD2*vvout - ipk*Lf
v_zero_Dtrf = - vDon + vDch + vDtrf

} # end of values section

equations {

i(zero_D2->com) += i_zero_D2
i_zero_D2 : v(zero_D2) - v(com) = v_zero_D2

i(zero_Dtrf->com) += i_zero_Dtrf
i_zero_Dtrf : V(zero_Dtrf) - v(com) = v_zero_Dtrf

i(i_equiv->com) += i_iequi
i_iequi : v(i_equiv) - v(com) = v_iequiv

i(i_deviat->com) += i_ideviat
i_ideviat : v(i_deviat) - v(com) = v_ideviat

i(v_equiv->com) += i_vequi
i_vequi : v(v_equiv) - v(com) = v_vequiv

} # end of equations section

} # end of template body

198
B2. New Model

element template zvs_duo_2_rev2_4a com ilf vout vin Don

Dtrf D2 i_equiv v_equiv i_deviat zero_Dtrf zero_D2 I1out
I3out = Ts, Lf, Llk, N

electrical com, ilf, vout, vin, Don, Dtrf, D2, i_equiv,

v_equiv, i_deviat, zero_Dtrf, zero_D2, I1out, I3out

number Ts, Lf, Llk, N

{
val v delta_ilf, deltaup, deltadwn, ipk, d_off, vilf,
vvout, vvin, vDon, vDch, vDtrf, vDoff, vD2,vDtrf1, AA, BB,
CC,
v_vequiv, v_iequiv, v_ideviat, v_zero_D2,
v_zero_Dtrf, m1, m2,m3, m4, IX, IY, IZ, IW, Lequiv, NTS

var i i_iequi, i_vequi, i_ideviat, i_zero_D2, i_zero_Dtrf,

i_I1out, i_I3out

values {
vilf = v(ilf)-v(com)
vvout = v(vout)-v(com)
vvin = v(vin)-v(com)
vDon = v(Don)-v(com)
vDtrf = v(Dtrf)-v(com)
vD2 = v(D2)-v(com)

Lequiv = Lf + Llk/N**2

NTS = N*Ts

m1 = (vvin/N-vvout)/Lequiv
m2 = vvout/Lequiv
m3 = vvout/Lf
m4 = vvin*N/Llk

if ( vD2 >= 0 & vD2 <= 1-vDon ) {

NTS = N*Ts
}
else {
if ( vD2 <= 0 ) {
vD2 = 0

199
 }
else {
vD2 = 1-vDon
}
}

if ( vilf > m1*vDtrf*Ts/2 | m1*vDtrf > m2*(1-vDon) ) {

AA = -(m3+m1)

BB = m4-vDoff*(2*m1-
m3)+m3*vDon

CC = vDoff*(m2*vDoff+m3*vDon)-
m4*vDon+2*vilf/Ts

v_zero_Dtrf = -AA*vDtrf**2 -
BB*vDtrf - CC

vDoff = 1 - vDon
vDch = vDon - vDtrf

IY = (m4-m3)*vDch*TS/2
IX = IY + m1*vDtrf*TS
IW = IX - m2*vDoff*TS
IZ = IY + m3*vDch*TS

v_vequiv = vvin*vDtrf/N
v_iequiv = ((-
IZ+IY)*vDch/2+(IY+IX)*vDtrf/2)/N
v_ideviat = (IY+IY)*vDch/2
v_zero_D2 = TS*vD2*m2 - IX
}

else {
v_zero_D2 = TS*vD2*m2*(vDtrf+vD2)-2*vilf
v_iequiv = vilf*vDtrf/(vDtrf+vD2+1e-10)/N
v_ideviat =0

v_vequiv = vvin*vDon/(vDon+vD2+1e-10)/N
}

} # end of values section

200
equations {

i(zero_D2->com) += i_zero_D2
i_zero_D2 : v(zero_D2) - v(com) = v_zero_D2

i(zero_Dtrf->com) += i_zero_Dtrf
i_zero_Dtrf : V(zero_Dtrf) - v(com) = v_zero_Dtrf

i(i_equiv->com) += i_iequi
i_iequi : v(i_equiv) - v(com) = v_iequiv

i(i_deviat->com) += i_ideviat
i_ideviat : v(i_deviat) - v(com) = v_ideviat

i(v_equiv->com) += i_vequi
i_vequi : v(v_equiv) - v(com) = v_vequiv

i(I1out->com) += i_I1out
i_I1out : v(I1out) - v(com) = IX

i(I3out->com) += i_I3out
i_I3out : v(I3out) - v(com) = IY

} # end of equations section

} # end of template body

201
C Analysis and Design Procedure of Saturable Reactor-Based Zero-
Voltage Zero-Current Switched, Full-Bridge PWM Converter
and Saber Template for its Average Model

C1. Introduction

This appendix presents general design procedure for the high power, high
performance ZVZCS-FB-PWM converter.

Verification of design procedure is performed through both numerical solution of

exact steady-state nonlinear equations and experimental implementation of a practical
design example. The latter corresponds to a specific application: 10 kW, three-module,
dc-dc system operating at 100 kHz.

C2. Review of Steady State Operation

Fig. C1 shows major topological stages for steady state operation of the ZVZCS
converter, i.e. Blocking, Charging, Transfer, Resetting and Off, whose characteristics are
summarized below.

Blocking Stage. Starts at t0 when Vin is applied between nodes a and b, and ends at
t1 when the saturable reactor stops blocking any current. On the primary side, the sum of
input voltage and the blocking capacitor voltage determines the rate of change of flux in
the saturable reactor, while on the secondary side, the output voltage (assumed constant
throughout the appendix) determines rate of change of current through the filter inductor,
Lf.
Charging Stage. Starts at t1 when current begins to flow on primary side and ends
at t2 when primary current equals reflected filter inductor current. Secondary side
conditions remain the same as in the previous stage.

Transfer Stage. Starts at t2 after primary current equals reflected filter inductor
current with transformer in normal operation, and ends at t3 when Vab becomes zero.
Resetting Stage. Starts at t3 when Vab becomes zero and ends at t4 when primary
current becomes zero. Once again primary and secondary side are independent from one
another.

Off stage. Starts at t4 when primary current becomes zero and saturable reactor
takes all blocking capacitor voltage as its flux rate of change, and ends at Ts when Vab
becomes -Vin.

202
 S1 S3 Lf
+ +
L s Cb Llk Vs If -
Vo
+ -
Vin
N:1
- a + -
b
Vcb Ip

S2 S4

S1 , S4 S2 , S 4 S2 , S3
Charging

Resetting
Blocking

Transfer

Off

Vab V in
D on ⋅ T s D on ⋅ T s

V cb Vcpk

m2
I p m3 I bus
m1 p I 3p
I 2

I 3f
N ⋅ m2
I m4
f
m4
I 2f I f I 4f

Vs
Vo

t0 t1 t2 t3 t4 t5 t

to t o + Ts

Fig. C1. ZVZCS converter and typical waveforms.

203
 For each stage, nonlinear equations relating initial and final values of the state
variables can be written. In order to form a complete set of equations two additional
equations are required: one including output power and one describing filter inductor
current ripple. This set, fully described in Equation Set I, will prove very useful later in
this work for development and verification of the dc model.

C3. Design Procedure

Having high closed-loop bandwidth as a major requirement forces the switching

frequency to be very high. Since the ZVZCS topology is of forward type, its small-signal
loop-gain bandwidth can be expected up to one fifth of effective switching frequency. In
multi-module systems with interleaving the effective switching frequency is equal to the
product of the number of parallel modules and the frequency of each module.

After switching frequency selection, converter voltage and current levels will
determine the choice of semiconductor devices. Voltage stress for diodes on the
secondary side will mainly depend on transformer turns ratio and rectifier configuration
(center tap or full-bridge), as well as voltage ringing. The latter is due to diode reverse
recovery characteristics and its interaction with parasitics and snubbers.

In the following design procedure it is assumed that the line and load ranges are
known quantities and that the filter inductor current ripple and output voltage ripple are
specified.

Design of the ZVZCS converter involves complex interactions between device

characteristics, circuit parameters, and operating conditions. Therefore, the design has to
start from several assumptions or estimates which are then iteratively corrected as the
design proceeds. Let us first define duty-cycles of different operating stages in Fig. C1 as:

t 3 − t0
apparent: D= , (C.1)
Ts

t1 − t0
blocking: Dblk = , (C.2)
Ts

t 2 − t1
charging: Dch = , (C.3)
Ts

t3 − t2
transfer: Dtrf = , (C.4)
Ts

t4 − t3
resetting: Drs = , (C.5)
Ts

Ts − t 4
off: Doff = . (C.6)
Ts

204
 Although the primary circuit is operated with apparent duty-cycle, D, the
secondary duty-cycle, Dtrf, is smaller by the loss of duty-cycle, Dblk+Dch. During transfer
stage, the secondary rectifier output voltage is equal (Vin-Vcb)/N. Since the average value
of the blocking capacitor voltage is approximately zero during this time interval, the
output voltage is very closely given by

Vin ⋅ Dtrf
Vo = . (C.7)
N

The main design parameters are: transformer turns ratio, N, blocking capacitor
value, Cblk, and saturable inductor blocking capability. The first major assumption in the
design will be that it is desirable to have N as large as possible in order to minimize the
voltage rating of the secondary diodes as well as primary current peak value. Therefore it
is desirable to use maximum possible value of the transfer duty-cycle, Dtrfx. A reasonable
assumption for the first iteration could be

Dtrfx=0.8, (C.8)

which leaves 10% for the minimum off duty-cycle, Doffx, in order to provide sufficient
control authority during transients, and 10% for the sum of Dblk+Dch+Drs.

Second assumption that has to be made is the desired value of the peak blocking-
capacitor voltage Vcpk. Small values of Vcpk will increase the resseting time (transformer
leakage inductance is reset only by Vcpk) which will increase the primary current rms
value and limit maximum value of Dtrf. Large values of Vcpk will increase secondary
diode voltage rating, (Vin+Vcpk)/N, and decrease the duration of the charging stage which
will aggravate the secondary diode reverse recovery problems. Empirically determined
reasonable choice was found to be

Vcpk ≤ 0 .2 ⋅Vin . (C.9)

With assumptions (C.8) and (C.9) the first iteration of the design can be initiated.
The transformer turns ratio can be found from as
Vin min
N = ⋅ Dtrfx . (C.10)
Vo

Knowing N, Dtrfx, Vo, Ilf, and switching frequency provides sufficient information
for the transformer design. Once the transformer is designed, its leakage inductance, Llk,
can be estimated or measured. The transformer should be designed with minimum
leakage in order to increase the frequency of the ringing in the secondary caused by the
diode reverse recovery, so that it can be more easily suppressed with snubbers.

205
 Blocking capacitor, Cblk , is therefore estimated at low line and full load conditions
[C11] by
I lf max ⋅ Dtrfx ⋅ Ts
Cblk = . (C.11)
2 ⋅ N ⋅ Vcpk
ZCS operation in steady state requires volt-second blocking capability of saturable
reactor to be greater than the product Ts ⋅ Vcpk ⋅ Doff at high line and full load conditions.
Thus, the saturation flux of Ls should be

Doff max ⋅ Ts ⋅Vcpk

φ sat > . (C.12)
2 ⋅ N sr

where Nsr is the number of turns in Ls. However, ZCS operation during current limiting
situations demands higher volt-second values from the saturable reactor since the product
Ts ⋅ Vcpk ⋅ Doff becomes much larger than that in (C.12). Furthermore, should saturable
reactor allow oscillation between Llk and Cblk during off stage chaotic operation can occur
and lead to transformer saturation. Therefore, a safe value for the saturation flux of Ls
could be chosen as

Ts ⋅Vcpk
φ sat = . (C.13)
2 ⋅ N sr

At this moment the design should be checked against the original assumptions.

During the resetting stage, the primary current reduces with the slope of Vcpk/Llk,
so that

Drs =
(I lf )
+ ∆I lf ⋅ Llk
, (C.14)
N ⋅ Ts ⋅Vcpk
where ∆I lf is the filter inductor current ripple specification.

During charging stage, the primary current increases with the slope of
(Vin+Vcpk)/Llk, and hence

Dch =
(I lf )
− ∆I lf ⋅ Llk
. (C.15)
(
N ⋅ Ts ⋅ Vin + Vcpk )

During off time the primary current is kept at zero by the saturable inductor Ls
with the voltage across it equal to Vcpk. In the following blocking stage, the voltage across
Ls increases to Vin+Vcpk so that the blocking stage duty-cycle can be found as

206
 1  2 ⋅ φ sat 
Dblk = ⋅ − Doff ⋅ Vcpk  (C.16)
Vin + Vcpk  N sr ⋅ Ts 

where it is assumed that

Doffx=0.1. (C.17)

Now, the assumption (A.8) can be verified against

Dtrfx = 1 - Drs - Dch - Doffx - Dblk . (C.18)

Additionally, in order to assure minimum turn-on loss in the lagging leg, i.e.
complete zero-current turn-off, duration of off stage must be longer than the switch turn-
off time [C11]. A reasonable assumption could be

Toff + Ttail
Drs = 1.5 ⋅ , (C.19)
Ts

where Toff and Ttail are IGBT parameters for full load, and Ttail ≈ 0 for MOSFETs.

If there is only small discrepancy between the assumptions (C.8) and (C.19) and
the results (C.18) and (C.14), it usually can be easily adjusted by changing the values of
Cblk and Vcpk. However, large differences may require changes in the transformer design
(N and Llk), and even change of the switching frequency or selection of active devices.

The design of the output filter is quite straightforward. Lf is normally determined

by current ripple specifications unless very strong output impedance and large signal
requirements make it irrelevant. Considering the first one, Lf must satisfy

Lf ≥
(
Vo ⋅ 1 − Dtrfx )− L lk
. (C.20)
2 ⋅ ∆I lf N2
Filter capacitor is normally calculated from voltage ripple requirements but
stringent output impedance specifications might override them. Assuming the former as
determining factor, its value is given by

∆I lf ⋅ Ts
Cf = 2
, (C.21)
2 ⋅ module ⋅ ∆Vo

207
where ∆Vo is peak to peak output voltage ripple and module is the number of paralleled
interleaved modules.

It is worth noting that if the output voltage were to vary over a wide range,
additional conditions, listed in Table C1, will have to be considered in the design
procedure.

Table C1. CONDITIONS FOR PARAMETER SELECTION

Li Output Output
ne Voltage Current
Transformer Lo High Maximu
Turns Ratio w m
Blocking Lo High Maximu
Capacitor w m
Saturable Hi Low Maximu
Reactor gh m
Filter Inductor  V2 
max of Vo − o ⋅ N 
 Vin 

Example: The ZVZCS converter shown in Fig. C1 is designed for the following
specifications

Vin : 280 − 480 V , Vo =33 V , Po = 3.3 kW ,

∆I f ≤ 30 A , ∆Vo ≤ 20 mV, f s = 100 kHz . .

Using the design procedure given above, following components are selected:

N = 6 , Llk = 1µH, Cblk = 1µF,

φ sat ⋅ N sr = 60 µV − s, L f = 2 µH , C f = 200 µF.

C3. DC Analysis

As stated above, dc voltage conversion ratio for the ZVZCS converter is almost
entirely determined by transformer turns ratio and transfer duty-cycle. This is verified by
calculating the voltage conversion ratio, for the converter parameters in the above
example, using the exact nonlinear steady-state equations given in Equation Set I. As can

208
be seen from Fig. C2, the ratio is practically independent from input voltage and output
power levels. It is interesting to note that this is true even though the blocking-capacitor
peak voltage and peak primary current vary considerably with input voltage and output
power, as shown in Fig. C3. The same figure also compares the results obtained by using
approximate equations in Equation Set III with those obtained from exact non-linear
equations in Equation Set I. As can be seen, at least for the numerical values from the
example, there is very small disagreement between the two sets.

Therefore, the dc model is the same as buck converter model except that the
switch duty-cycle (named here apparent duty-cycle, D) is replaced with the transfer duty-
cycle, as shown in Fig. C4. Using simplified equations, it is derived in Equation Set II
that the transfer duty-cycle is given by

2 ⋅ Llk
D ⋅ Vin ⋅ Ts − 2 ⋅ φ sat ⋅ N sr − ⋅ I lf
Dtrf = N (C.22)
Vin ⋅ Ts −
( 1 − D) ⋅ Ts2 ⋅ I
lf
2 ⋅ N ⋅ Cblk

It follows from (C.24) that the presence of Ls, Llk, and Cblk, introduces
feedforward from Vin and feedback from Ilf into the open-loop model of the ZVZCS
converter, similarly as in the ZVS-FB converter [V5].

However, unlike in the ZVS, the inductor current feedback in the ZVZCS
converters can be positive. From (C.22) if

 2 ⋅ φ sat ⋅ N sr  Llk ⋅ Cblk

( 1 − D)  D −  > 2⋅ (C.23)
 Vin ⋅ Ts  Ts

the transfer duty-cycle increases with the inductor current, resulting in positive feedback.
Since Llk and Cblk are much smaller in ZVZCS than in ZVS converters, condition (C.23)
is satisfied in most cases. It is also important to note that (C.23) is a conservative
condition due to the approximations used in the estimate for Vcpk, and described in
Equation Set II.

The above phenomenon can be further explored by analyzing the loss of duty-
cycle,

D − Dtrf = Dblk + Dch , (C.24)

for the ZVZCS converter. Fig. C5 shows dependence of the blocking and charging duty-
cycles on the output power, i.e. average filter inductor current. Even though increase in
duration of the charging stage takes place as expected and confirmed by Fig. C5, use of a
lower Cblk value in the ZVZCS converter, as compared to that in the ZVS converter,
allows a strong rise in Vcpk with Po to take place, as it is clearly seen in Fig. C3. This in

209
turn makes the product Vcpk ⋅ Doff ⋅ Ts larger, which leads to a reduction in blocking stage
duration, since saturable-reactor volt-second blocking capability is constant. At the end,
this reduction counteracts for the increase in charging stage duration and produces the
reduction in duty-cycle loss. The size of that reduction will strongly depend on blocking
capacitor value and saturable reactor volt-second blocking capability. Furthermore, it is
possible to have increase in duty-cycle loss for some component values, especially when
they resemble those used in the ZVS converter.

C4. Experimental Results

Design values from the example were used to build a 10 kW, three-module, dc-dc
power converter operating at 100 kHz with current sharing and interleaving.

With three modules working in parallel, the experimental primary current

waveforms for low line and 40% load, and high line and 60% load conditions, are shown
in Fig. C6 where excellent current sharing is clearly observed. This is achieved through
simple and fast current injection control together with very good repeatability of
transformer characteristics provided by printed-circuit-board-type windings. This control
also provides the damping required to achieve as large closed-loop bandwidth as possible
[R4].

Fig. C7 shows Bode plots of voltage loop-gain transfer function for the three-
module power system operating at 60% load and Vin = 350 V, where crossover frequency
is about 25 kHz. Each module has its own local current loop and their reference is
provided by a common voltage loop.

The most severe problem in the converter operation is reverse recovery of the
secondary diodes, as can be clearly seen in Fig. C6. Since the leakage inductance is so
small, the slope of the rectifier current reversal during charging stage is very steep.
Therefore, rectifier snubber design and its layout are extremely important when dealing
with reverse recovery effects at high currents. Fig. C8 shows voltage waveforms across
one of the rectifiers for two different snubber layouts, Vin=400V, and 100 A load. The big
improvement in peak reduction comes from having the snubber placed right on top of
rectifier which minimizes parasitics in the snubber itself. Even though this made duration
of transfer stage in the primary side look longer, its duration on the secondary side
followed predictions very closely.

210
 0.8 0.55

D trf =0.8
D trf =0.5 0.5

0.7

0.45

0.6
0.4
N Vo D trf =0.6 N Vo D trf =0.375
V in V in
0.35
0.5

0.3

0.4
Dtrf =0.25
Dtrf =0.4 0.25

1000 2000 3000 0.3 1000 2000 3000 0.2

Po Po

(a) low line (b) high line

Fig. A2. Voltage conversion ratio.

40 40

D=0.775 D=0.416
35 35

V
Cpk
30 30

V Cpk
25 25

20 20

Ipri-pk
15 15
I pri-pk

10 10

500 1000 1500 2000 2500 3000 3500

5 500 1000 1500 2000 2500 3000 3500
5

Po Po

(a) low line (b) high line

Fig. C3. Blocking-capacitor peak voltage, peak primary current for exact (solid) and
approximate (dotted) equations.

211
 Lf

Vin +
+ Vo
N

1 : Dtrf

Fig. C4. Dc model for ZVZCS converter.

7 7

D=0.775 D=0.416
6 6

D blk
5 5

4 4

D blk
3 3

2 2

1 1
D ch
D ch

500 1000 1500 2000 2500 3000 3500

0 500 1000 1500 2000 2500 3000 3500
0

Po Po

(a) low line (b)high line

Fig. C5. Duty-cycles of blocking and charging stages for exact (solid) and approximate
(dotted) equations.

212
 Vertical : 5A / div Horizontal : 2 µs / div

(a) Low line, 40% load (b) High line, 60% load
Fig. C6. Experimental primary currents from 3-module dc-dc power system with
interleaving.

80
Magnitude (db)

60

-40

-45

-90
Phase (deg)

-135

-180

-225

0.1 1 10 100
Frequency (kHz)

Fig. C7. Voltage loop-gain for the 3-module dc-dc power system at Vin=350 V and 6 kW
resistive load.

213
 300 V

Normal
layout

0V

300 V

Optimal
layout

0V

Horizontal: 50 ns /div

Fig. C8. Voltage across rectifier for same snubber values but different layouts, at
Vin=400 V and 100 A load.

214
C5. Nomenclature

Vin, Vo: input and output voltages

Ilf : average output (filter inductor) current
Po: output power
Llk, Lf : primary leakage and filter inductors
Dblk, Dch, Dtrf, Drs, Doff : average value for blocking, charging, transfer, resetting and off
duty-cycles.
D: average apparent duty-cycle
Vcb1, Vcb2, Vcb3, Vcb4: blocking-capacitor voltage at t1, t2, t3, and t4 in Fig. 1, respectively
Ip2, Ip3: primary current at t2 and t3 in Fig. 1, respectively
Vcpk: estimate of blocking-capacitor peak voltage
φ sat : saturation flux of saturable inductor
∆φ off : change of flux in saturable reactor during off stage.
∆φ blk : change of flux in saturable reactor during blocking stage
N sr : turns in saturable reactor
N : primary to secondary turns ration
fs: switching frequency
Ts : switching period
Llk: primary leakage inductance
Cblk: blocking capacitor
Z1, ω1 : characteristic impedance and resonant frequency during charging and resetting
stages.
Z2, ω2 : characteristic impedance and resonant frequency during transfer stage

C6. Equation Set I

Steady-State Boundary Equations for Topological Stages

Blocking Stage:
Dblk ⋅ Ts ⋅ (Vin + Vcb1 )
∆φ blk = (CI-1)
N sr

Charging Stage:
Vin +Vcb1
I p2 = Z1 ⋅ sin(ω 1 ⋅ Dch ⋅ Ts ) (Ci-2)
Vcb 2 = (Vcb1 + Vin ) ⋅ cos(ω 1 ⋅ Dch ⋅ Ts ) − Vin (CI-3)
Z1 = Llk / Cblk (CI-4)
ω1 = 1/ Llk ⋅ Cblk (CI-5)

215
Transfer Stage:

(
I p 3 = I p 2 ⋅ cos ω 2 ⋅ Dtrf ⋅ Ts )
Vin − N ⋅ Vo + Vcb 2
+
Z2
(
⋅ sin ω 2 ⋅ Dtrf ⋅ Ts ) (CI-6)

(
Vcb3 = (Vcb2 +Vin − N ⋅Vo ) ⋅ cos ω2 ⋅ Dtrf ⋅ Ts )
(
−(Vin − N ⋅Vo ) − I p2 ⋅ Z2 ⋅ sin ω2 ⋅ Dtrf ⋅ Ts ) (CI-7)

4 
Z 2 =  ⋅ Llk + N 2 ⋅ L f  / Cblk (CI-8)
3 

4 
ω 2 = 1 /  ⋅ Llk + N 2 ⋅ L f  ⋅ Cblk (CI-9)
3 

(It is assumed that secondary leakage inductance reflected to the primary is half of Llk.)

Resetting Stage:

Vcb3
⋅ sin(ω 1 ⋅ Drs ⋅ Ts ) = I lk 3 ⋅ cos(ω 1n ⋅ Drs ⋅ Ts ) (CI-10)
Z1

Vcb 4 = −Vcb1 = Vcb 3 ⋅ cos(ω 1 ⋅ Drs ⋅ Ts )

− I lk 3 ⋅ Z1 ⋅ sin(ω 1 ⋅ Drs ⋅ Ts ) (CI-11)

Off Stage:

Vcb1 ⋅ Doff ⋅ Ts
∆φ off = (CI-12)
N sr

Filter Inductor Current Ripple:

(
Vo ⋅ 1 − Dtrf ⋅ Ts )
Llk ( )
= I p3 − I p2 ⋅ N (CI-13)
Lf +
N2

216
Output Power:

( )  + V ⋅ (1 − D )
2
 I p 3 ⋅ sin ω 2 ⋅ Dtrf ⋅ Ts
Po
Vo
( )
= N  I p 2 ⋅ 1 − Dtrf +
 ω 2 ⋅ Ts 
o

2⋅(L )
trf

  f

+
[ (
N ⋅ (Vin − N ⋅Vo + Vcb 2 ) ⋅ 1 − cos ω 2 ⋅ Dtrf ⋅ Ts )] (CI-14)
Z 2 ⋅ ω 2 ⋅ Ts

Saturable Reactor Total Flux Change:

2 ⋅ φ sat = ∆φ off + ∆φ blk (CI-15)

C7. Equation Set II

Average Dtrf in Steady-State

Simplified equations for computation of average Dtrf in terms of D after neglecting
inductor current ripple, Vcpk with respect to Vin, and contributions of charging and
resetting stages to Vcpk.

Doff = 1 − ( D + Drs ) (CII-1)

D = Dblk + Dch + Dtrf (CII-2)

2 ⋅ φ sat =
(D off ⋅Vcpk + Dblk ⋅Vin ⋅ Ts) (CII-3)
N sr

Llk ⋅ I lf
Dch = (CII-4)
N ⋅Vin ⋅ Ts

Llk ⋅ I lf
Drs = (CII-5)
N ⋅Vcpk ⋅ Ts

I lf ⋅ Dtrfx ⋅ Ts
Vcpk = (CII-6)
2 ⋅ N ⋅ Cblk

217
Solving (CII-1)-(CII-6)gives

2 ⋅ Llk
D ⋅Vin ⋅ Ts − 2 ⋅ φ sat ⋅ N sr − ⋅ I lf
Dtrf = N (CII-7)
Vin ⋅ Ts −
( 1 − D) ⋅ Ts2 ⋅ I
lf
2 ⋅ N ⋅ Cblk

C8. Equation Set III

Approximate Steady-State Equations

2 ⋅ φ sat =
[D off ⋅ Vcpk + Dblk ⋅ Vin + Vcpk( )] ⋅ Ts (CIII-1)
N sr

Dch =
(
Llk ⋅ I lf − ∆I lf ) (CIII-2)
(
N ⋅ Vin + Vcpk ⋅ Ts )

Drs =
(
Llk ⋅ I lf + ∆I lf ) (CIII-3)
N ⋅Vcpk 2 ⋅ Ts

Vo ⋅ N
Dtrf = (CIII-4)
Vi

∆ ilf =
( )
Vin ⋅ 1 − Dtrf ⋅ Dtrf ⋅ Ts
(CIII-5)
 L 
N ⋅  L + ⋅ lk2 
 N 

Po = Vo ⋅ I lf (CIII-6)

218
C9. Listing of Saber templates for New Model of ZVZCS-FB PWM
Converter

C9.1 Template 1.

This template calculates charging and resetting duty-cycles, average

controlled-voltage source, peak blovcking-capacitor voltage and flux constraint
equation.

element template dchrsdeviaveffcpkzero com In1 In2 In3 In4

In5 In6 In7 in8 Out1 Out2 Out3 Out4 Out5 Out6 = Ts, Lf,
Llk, Cblk, N, phi_sat

electrical com, In1, In2, In3, In4, In5, In6, In7, In8,
Out1, Out2, Out3, Out4, Out5, Out6

number Ts, Lf, Llk, Cblk, N, phi_sat

{
val v v1, v2, v3,v4, v5, v6, v7, v8, ilf, Dtrf, Doff, Dblk,
ipk, ivall, delta_ilf, vin, vcpk, Lequiv, Zo, Wo, Dch, Drs,
Idevia, veff, zero_satu,
v_out1, v_out2, v_out3, v_out4, v_out5, v_out6

var i i_Out1, i_Out2, i_Out3, i_Out4, i_Out5, i_Out6

values {

v1 = v(In1)-v(com)
v2 = v(In2)-v(com)
v3 = v(In3)-v(com)
v4 = v(In4)-v(com)
v5 = v(In5)-v(com)
v6 = v(In6)-v(com)
v7 = v(In7)-v(com)
v8 = v(In8)-v(com)

Lequiv = Lf + Llk/N**2

Zo = (Llk/Cblk)**0.5
Wo = 1/(Llk*Cblk)**0.5

219
ilf = v1
Dtrf = v2
ipk = v3
ivall = v4
delta_ilf = v5
vin = v6
Doff = v7
Dblk = v8

vcpk = ilf*Dtrf*Ts/(2*N*Cblk) +
(ilf+delta_ilf/2)*Llk/(2*N*Ts)

Dch = (ilf-delta_ilf/2)*Llk/(vin+vcpk)/N/Ts

Drs = Llk*(ilf+delta_ilf/2) / (vcpk*N*Ts+1e-10)

Idevia = (1 - Dtrf)*ilf

veff = vin*Dtrf/N + ilf*Llk/(2*N**2*Ts)

zero_satu = phi_sat/Ts - Doff*vcpk - (vin + vcpk)*Dblk

v_out1 = Dch
v_out2 = Drs
v_out3 = Idevia
v_out4 = veff
v_out5 = vcpk
v_out6 = zero_satu

} # end of values section

equations {

i(Out1->com) += i_Out1
i_Out1 : v(Out1) - v(com) = v_Out1

i(Out2->com) += i_Out2
i_Out2 : v(Out2) - v(com) = v_Out2

i(Out3->com) += i_Out3
i_Out3 : v(Out3) - v(com) = v_Out3

i(Out4->com) += i_Out4
i_Out4 : v(Out4) - v(com) = v_Out4

220
 i(Out5->com) += i_Out5
i_Out5 : v(Out5) - v(com) = v_Out5

i(Out6->com) += i_Out6
i_Out6 : v(Out6) - v(com) = v_Out6

} # end of equations section

} # end of template body

C9.2 Template 2.

This template calculates blocking and off duty-cycle, and peak and valley
values for primary current.

element template pkvaldeltablkoff com In1 In2 IN3 In4 In5

In6 In7 Out1 Out2 Out3 Out4 Out5 = Ts, Lf, Llk, Cblk, N,
phi_sat

electrical com, In1, In2, IN3, In4, In5, in6, iN7, Out1,
Out2, Out3, Out4, Out5

number Ts, Lf, Llk, Cblk, N, phi_sat

val v v1, v2, v3, v4, v5, v6, v7, ilf, vin, vout, Don, Dch,
Drs, Dtrf, Dblk, Doff, delta_up, delta_dwn, delta_ilf,
Lequiv,
Zo, Wo, ipk, ivall, v_out1, v_out2, v_out3, v_out4,
v_out5

var i i_Out1, i_Out2, i_Out3, i_Out4, i_Out5

values {
v1 = v(In1)-v(com)
v2 = v(In2)-v(com)

221
v3 = v(In3)-v(com)
v4 = v(In4)-v(com)
v5 = v(In5)-v(com)
v6 = v(In6)-v(com)
v7 = v(In7)-v(com)

Lequiv = Lf + Llk/N**2

Zo = (Llk/Cblk)**0.5
Wo = 1/(Llk*Cblk)**0.5

vin = v1
vout = v2
ilf = v3
Dtrf = v4
Don = v5
Dch = v6
Drs = v7

delta_up = (vin/N-vout)*Dtrf*TS/Lequiv
delta_dwn = vout*(1-Dtrf)*Ts/Lf

delta_ilf = delta_up

Dblk = Don - Dch - Dtrf

Doff = 1 - Don - Drs

ipk = ilf + delta_ilf/2

ivall = ilf - delta_ilf/2

v_out1 = ipk
v_out2 = ivall
v_out3 = delta_ilf
v_out4 = Dblk
v_out5 = Doff

} # end of values section

equations {

i(Out1->com) += i_Out1
i_Out1 : v(Out1) - v(com) = v_Out1

222
 i(Out2->com) += i_Out2
i_Out2 : v(Out2) - v(com) = v_Out2

i(Out3->com) += i_Out3
i_Out3 : v(Out3) - v(com) = v_Out3

i(Out4->com) += i_Out4
i_Out4 : v(Out4) - v(com) = v_Out4

i(Out5->com) += i_Out5
i_Out5 : v(Out5) - v(com) = v_Out5

} # end of equations section

} # end of template body

223
D Modified Equations for Cases 2 and 3 of QSS-ZVZCS
Three-Phase Buck Rectifier Operation and for
Compensated First Duty-Cycle for Case 1

D1. Modified Constraint Equations for Case 2

 Vline1 + Vcpk 
I 2p =  (t 2 − t1 )⋅ = (m1) ⋅ (Dch1 ⋅ Ts ) , (D1.9)
 LLk 

I 2f ≠ I 2p ⋅ N , (D1.10)

I 3f = I 3p ⋅ N , (D1.10.a)

d 1 ⋅ Ts = (t 2 − t 0 ) == (Dblk + Dch1 ) ⋅ Ts . (D1.11)

 
 − V0 
I −I =  ⋅ (t 3 − t 2 )⋅ = ( N ⋅ m4 ) ⋅ (Dch 2 ⋅ Ts ) ,
f f
3 2 (D1.12)
 Llk 2 + L f 
 N 

 Vac 
 − V0 
 ⋅ (t 4 − t 3 )⋅ = ( N ⋅ m3 ) ⋅ (Dtrf 2 ⋅ Ts )
I 4f − I 3f =  N (D1.13)
 Llk 2 + L f 
 N 

1  Ip Llk 
t 5 − t 4 = Dres ⋅ Ts = ⋅ arcsin 4 ⋅ . (D1.14)
LLk ⋅ C Blk V Cblk 
 Cpk 

Vcpk ⋅ (1 − d 1 − d 2 − Dres ) ⋅ Ts
∆ φoff = , (D1.15)
N sr

∆ φblk = 2 ⋅ φ sat − ∆ φoff , (D1.16)

224
 I L ⋅ (Dtrf 2 )⋅ Ts
∆ Vc −trf = (D1.17)
N ⋅ Cblk

∆ Vc −res =
(I ) ⋅ L
4
f 2
lk
, (D1.18)
N ⋅ I ⋅ (D )⋅ T
L trf 2 s

∆ Vc−trf + ∆ Vc−res
Vcpk = . (D1.19)
2

IL =
1
2
[ ( )
⋅ Dtrf 2 ⋅ I 4f + I 3f + (1 − Dtrf 2 )⋅ I 5f + I 4f , ( )] (D1.20)

V 
(I 5
f
)
− I 4f =  0
L
 ⋅ (1 − Dtrf 2 )⋅ Ts = m4 ⋅ (1 − Dtrf 2 )⋅ Ts ,

(D1.21)
 f 

Vs 1 = 0 (D1.22)

Vline 2 + Vcb L
⋅ L f + V0 ⋅ lk2
Vs 2 = N N , (D1.23)
Llk
+ Lf
N2

Vline 2 ⋅ Dtrf 2  
 ⋅ (Dtrf 2 )
L V
⋅ L f + V0 ⋅ lk2 + cb ⋅ L f 
N  N N 
Vs = (D1.24)
Llk
+ Lf
N2

I L ⋅ (Dtrf 2 )⋅ TS
Vcb = Vcpk − . (D1.25)
2 ⋅ N ⋅ Cblk

I 2p
I phase1 = ⋅ Dch1 (D1.26)
2

I phase 2 =
(I 2
p
+ I 3p )
⋅ Dch 2 +
(
I 3p + I 4p )
⋅ Dtrf 2 . (D1.27)
2 2

225
D2. Modified Constraint Equations for Case 3

 Vline1 + Vcpk  V + Vcpk 

∆φblk = (t1 − t0 ) ⋅   + (t 2 − t1 ) ⋅  line 2  =
 N sr   N sr 
(D2.8)
V +V  V +V 
(Dblk 1 ⋅ Ts ) ⋅  line1 cpk  + (Dblk 2 ⋅ Ts ) ⋅  line 2 cpk  ,
 N sr   N sr 

I 2p = 0 , (D2.9)

I 2f ≠ I 2p ⋅ N , (D2.10.a)

I 3f ≠ I 3p ⋅ N , (D2.10.b)

I 4f = I 4p ⋅ N , (D2.10.c)

d 1 ⋅ Ts = (t1 − t0 ) == (Dblk 1 ) ⋅ Ts . (D2.11.a)

d 2 ⋅ Ts = (t 3 − t1 ) == (Dblk 2 + Dch 3 + Dtrf 3 )⋅ Ts . (D2.11.b)

 
 − V0 
I −I =  ⋅ (t 3 − t 2 )⋅ = ( N ⋅ m4 ) ⋅ (Dch 3 ⋅ Ts ) ,
f f
3 2 (D2.12)
 Llk 2 + L f 
 N 

 Vac 
 − V0 
 ⋅ (t 4 − t 3 )⋅ = ( N ⋅ m3 ) ⋅ (Dtrf 3 ⋅ Ts )
I −I =
f f N (D2.13)
4 3
 Llk 2 + L f 
 N 

1  Ip Llk 
t 5 − t 4 = Dres ⋅ Ts = ⋅ arcsin 4 ⋅ . (D2.14)
LLk ⋅ C Blk  
 VCpk Cblk 

Vcpk ⋅ (1 − d 1 − d 2 − Dres ) ⋅ Ts
∆ φoff = , (D2.15)
N sr

∆ φblk = 2 ⋅ φ sat − ∆ φoff , (D2.16)

226
 I L ⋅ (Dtrf 3 )⋅ Ts
∆ Vc −trf = (D2.17)
N ⋅ Cblk

∆ Vc −res =
(I ) ⋅ L
4
f 2
lk
, (D2.18)
N ⋅ I ⋅ (D )⋅ T
L trf 3 s

∆ Vc−trf + ∆ Vc−res
Vcpk = . (D2.19)
2

IL =
1
2
[ ( )
⋅ Dtrf 3 ⋅ I 4f + I 3f + (1 − Dtrf 3 )⋅ I 5f + I 4f , ( )] (D2.20)

V 
(I 5
f
− I 4f ) =  0
L
 ⋅ (1 − Dtrf 3 )⋅ Ts = m4 ⋅ (1 − Dtrf 3 )⋅ Ts ,

(D2.21)
 f 

Vs 1 = 0 (D2.22)

Vline 2 + Vcb L
⋅ L f + V0 ⋅ lk2
Vs 2 = N N , (D2.23)
Llk
+ Lf
N2

Vline 2 ⋅ Dtrf 3  
 ⋅ (Dtrf 3 )
L V
⋅ L f + V0 ⋅ lk2 + cb ⋅ L f 
N  N N 
Vs = (D2.24)
Llk
+ Lf
N2

I L ⋅ (Dtrf 3 )⋅ TS
Vcb = Vcpk − . (D2.25)
2 ⋅ N ⋅ Cblk

I phase1 = 0 (D2.26)

I phase =
I 3p
⋅ Dch 3 + 3
(
I p + I 3p
⋅ Dtrf 3
) (D2.27)
2 2

227
D3. Simplified Equations for Compensated First Duty-Cycle in Case 1

Simplified equations for computation of applied D1 in terms of Dtrf after

neglecting Vcpk with respect to Vin, and contributions of charging and resetting stages to
Vcpk.

Dblk ⋅ Ts ⋅ Vline1
∆φblk = (1.b)
N sr

I L ⋅ Llk
Dch ⋅ Vline1 = , (2.b)
N ⋅ Ts

Dtrf 1 = d1 − Dblk − Dch . (4.b)

Llk ⋅ I L
Dres = (7.b)
N ⋅ Vcpk ⋅ Ts

I L ⋅ (Dtrf 1 + d 2 ) ⋅ Ts
Vcpk = (8.b)
2 ⋅ N ⋅ Cblk

Vcpk ⋅ Doff ⋅ Ts
∆φoff = , (9.b)
N sr

2 ⋅ φsat = ∆φoff + ∆φblk . (10.b)

Doff = 1 − (d1 + d 2 + Dres ) . (11.b)

Solving this set gives

2 ⋅ φ sat ⋅ N sr I lf  Ts ⋅ (1 − d 2 ) ⋅ (Dtrf 1 + d 2 ) 2 ⋅ Llk 

Dtrf 1 + −  − 
Vin1 ⋅ Ts ⋅N  2 ⋅ Cblk ⋅ Vin1 Ts ⋅ Vin1  (17.b)
d1 =
I lf ⋅ Ts ⋅ (Dtrf 1 + d 2 )
1−
2 ⋅ Cblk ⋅ Vin1 ⋅ N

where Dtrf 1 = D pri1 is the desired primary duty-cycle.

228
VITA

Carlos Eduardo Cuadros O. was born August 3, 1958 in Palmira Colombia. He

received the Ingeniero Electronico degree in 1982 from Pontificia Universidad Javeriana,
Bogota, Colombia, where he was also a research and teaching associate from 1982 to
1985, and a Master of Science in electrical Engineering from Virginia Polytechnic
Institute and State University in 1998.

From 1985 to 1991 he worked for Lab-Volt Systems, NJ as a Field Engineer in

their Ecuadorian division and from 1999 to 2003 he was a design engineer with Dynamic
Structures and Materials, Franklin, Tennessee.

His current research interest is design, modeling an control of dc to dc, three-

phase to dc and dc to three-phase uni- and bi-directional soft-switching converters.

229