| SAA1099 MICROPROCESSOR CONTROLLED STEREO SOUND GENERATOR FOR SOUND EFFECTS AND MUSIC SYNTHESIS GENERAL DESCRIPTION The SAA1099 is a monolithic integrated circuit designed for generation of stereo sound effects and music synthesis, Features © Six frequency generators eight octaves per generator 256 tones per octave © Two noise generators © Six noise/frequency mixers © Twelve amplitude controllers ‘© Two envelope controllers ‘© Two 6-channel mixers/current sink analogue output stages © TTL input compatible © Readily interfaces to 8-bit microcontroller © Minimal peripheral components © Simple output filtering Applications ‘© Consumer games systems ‘© Home computers © Electronic organs © Arcade games © Toys © Chimes/alarm clocks QUICK REFERENCE DATA Supply voltage (pin 18) Voo typ. SV Supply current (pin 18) Ipp typ. 70 mA Reference current (pin 6) lref typ. 250 HA Total power dissipation Prot 500 mW Operating ambient temperature range Tamb Oto +70 OC PACKAGE OUTLINE 18-lead DIL; plastic (SOT 102), November 1986 413SAA1099 J L “uresBeip xo01g 1 ‘Bl i jf earrouinco Jef ear0an03 k_T ran Sowa. | Sate’ = aur) woLwyaNa0 zouis cee] Sedo” [apne vee «|_| iro vwaroun Tram LLL [rsonmaos = om |e Say Ses =H |. —_ serie oats le vemounc> Je_L von 30nLnawy i z pond Tame Se = ‘suania OUITIOUINOD }4#—] ESTIONINOD 2 MOLWUANED a SNe J.J Bowe? | Sarat |] ‘Ranonee vet verrounc> |e_Toam LLL iecamanso wo ot. cairns Sanebes t el | 609 Jef sem LL [oupumanan von von spends wos, t " 1.1 comme | one | meoore WOLYYANID aon oe IS Ie = 21001 | Sto vasa] [cena] [sure ~ 2 om ana mnMicroprocessor controlled stereo sound generator SAA1099. for sound effects and music synthesis PINNING Yoo 07 06 05. saswos [ia]o4 03 race 02 vor Ta] 00 Fig. 2 Pinning diagram. PIN DESIGNATION 1 wR Write Enable: active LOW input which operates in conjunction with CS and AO to allow writing to the internal registers. 2 cs Chip Select: active LOW input to identify valid WR inputs to the chip. This input also operates in conjunction with WR and AO to allow writing to the internal registers. 3 AO Control/Address select: input used in conjunction with WR and CS to load data to the control register (AO = 0) or the address buffer (AO = 1) 4 OUTR Right channel output: a 7-level current sink analogue output for the ‘right’ component, This pin requires an external load resistor. 5 OUTL Left channel output: a 7-level current sink analogue output for the ‘left’ component, This pin requires an external load resistor. lef Reference current supply: used to bias the current sink outputs. 7 DTACK Data Transfer Acknowledge: open drain output, active LOW to acknowledge successful data transfer. On completion of the cycle DTACK is set to inactive. 8 cLK Clock: input for an externally generated clock at a nominal frequency of 8 MHz. 9 Vss Ground: 0 V. 10-17 DO-D7_—_Data: Data bus input. 18 Voo Power supply: + 5 V typical November 1986 415SAA1099 J L FUNCTIONAL DESCRIPTION ‘The following sections provide a detailed functional description of the SAA1099 as shown in the block diagram, Fig. 1. Frequency generators Six frequency generators can each select one of 8 octaves and one of 256 tones within an octave. A total frequency range of 31 Hz to 7,81 kHz is available. The outputs may also control noise or envelope generators. Alll frequency generators have an enable bit which switches them on and off, making it possible to preselect a tone and to make it inaudible when required. The frequency generators may be synchronized using the frequency reset bit. The frequency ranges per octave are Octave Frequency range 0 31 Hz to 61 Hz 61 Hz to 122 Hz 122 Hz to 244 Hz 245 Hz to 488 Hz 489 Hz to 977 Hz 978 Hz to 1,95 kHz 1,96 kHz to 3,91 kHz 3,91 kHz to 7,81 kHz Moonen Noise generators The two noise generators both have a programmable output. This may be a software controlled noise via one of the frequency controlled generators or one of three pre-defined noises, There is no tone produced by the frequency generator when it is controlling the noise generator. The noise produced is based on double the frequency generator output, i.e. a range of 61 Hz to 15,6 kHz. In the event of a pre-defined noise being chosen, the output of noise generator O can be mixed with frequency generator 0, 1 and 2; and the output of noise generator 1 can be mixed with frequency generator 3, 4 and 5, In order to produce an equal level of noise and tone outputs (when both are mixed) the amplitude of the tone is increased. The three pre-defined noises are based on a clock frequency of 7,8 kHz, 15,6 kHz or 31,25 kHz, Noise/frequency mixers Six noise/frequency mixers each with four selections © Channel off © Frequency only © Noise only © Noise and frequency Each mixer channel has one of the frequency generator outputs fed to it, three channels use noise generator 0 and the other three use noise generator 1. Amplitude controllers Each of the six channel outputs from the mixer is split up into a right and left component giving effectively twelve amplitude controllers. An amplitude of 16 possible levels is assigned to each of the twelve signals. With this configuration a stereo effect can be achieved by varying only the amplitude component. The moving of a sound from one channel to the other requires, per tone, only one update of the amplitude register contents. When an envelope generator is used, the amplitude levels are restricted. The number of levels available is then reduced to eight. This is achieved by disabling the least significant bit (LSB) of the amplitude control. 416 Novernber ~) (Microprocessor controlled stereo sound generator SAA1099 for sound effects and music synthesis Envelope controllers ‘Two of the six tone generators are under envelope control. This applies to both the left and right outputs from the tone generator, The envelope has the following eight possible modes: © Amplitude is zero Single attack Single decay Single attack-decay (triangular) Maximum amplitude Continuous attack Continuous decay Continuous attack-decay evccece The timing of the envelope controllers is programmable using one of the frequency generators (see Fig, 1). When the envelope mode is selected for a channel its control resolution is halved for that channel from 16 levels to 8 levels by rounding down to the nearest even level. There is also the capability of controlling the ‘right’ component of the channel with inverse of the ‘left! component, which remains as programmed, A direct enable permits the start of an envelope to be defined, and also allows termination of an envelope at any time, The envelope rate may be controlled by a frequency channel (see Fig. 1), or by the microprocessor writing to the address buffer register. If the frequency channel controlled is OFF (NE = FE = 0) the envelope will appear at the output, which provides an alternative ‘non-square’ tone capability. In this event the frequency will be the envelope rate, which provided the rate is from the frequency channel, will be a maximum of 1 kHz. Higher frequencies of up to 2 kHz can be obtained by the envelope resolution being halved from 16 levels to 8 levels. Rates quoted are based on the input of a8 MHz clock. Six-channel mixers/current sink analogue output stages Six channels are mixed together by the two mixers allowing each one to control one of six equally weighted current sinks, to provide a seven level analogue output. Command/control select In order to simplify the microprocessor interface the command and control information is multiplexed, To select a register in order to control frequencies, amplitudes, etc. the command-register has to be loaded The contents of this register determines to which register the data is written in the next control-cycle, If a continuous update of the control-register is necessary, only the control-information has to be written (the command-information does not change). If the command/control select (AO) is logic 0, the byte transfer is control; if AQ is logic 1, the byte transfer is command. Interface to microprocessor The SAA1099 is 2 data bus based I/O peripheral. Depending on the value of the command/control signal (AO) the CS and WR signals control the data transfer from the microprocessor to the SAA1099. The data-transfer-acknowledge (DTACK) indicates that the data transfer is completed. When, during the write cycle, the microprocessor recognizes the DTACK, the bus cycle will be completed by the processor. November 1986 417SAA1099 RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Supply voltage (pin 18) Vop Maximum input voltage vi at Vpp = 4,5 to 5,5 V vy Maximum output current lo Total power dissipation Prot Storage temperature range Tstg Operating ambient temperature range Tamb Electrostatic handling* Ves * Equivalent to discharging 2 250 uF capacitor through a 1 k& series resistor. -0,3t0 +75 -03t0 +75 \5t0 +75 max. 10 500 —86 to +125 Oto +70 1000 to + 1000 << mA mw oc oc 418. November 1986Microprocessor controlled stereo sound generator for sound effects and music synthesis SAA1099 vE D.C. CHARACTERISTICS Vpp = 5 V + 10%; Tamb = 0 to 70 °C; unless otherwise specified parameter symbol min. typ. [max. June | Supply | i Supply voltage |Vop 45/50 |55 |v Supply current Ipp - 70 100 Ima | Reference current (note 1) ret 100 |250 400 | wa | | | INPUTS | | Input voltage HIGH ia 20 Ss leo vo} Input voltage LOW iL -05 |= los voi Input leakage current +t - - |o fua | Input capacitance ley = I- (10 |pr | outputs | | | | DTACK (open drain; note 2) | | | | Output voltage LOW | j | | | | atlo =3,2mA Vou 10 |- (0.4 lv | Voltage on pin 7 (OFF state) V7.9 |-0,3 |- 60 v | Output capacitance (OFF state) Co ie 10 pF Load capacitance cL |- - 150 pF Output leakage current (OFF state) -ILo |- 5 100 WA ‘Audio outputs (pins 4 and 5) | With fixed Ire¢ (note 3) | One channel on lotlret 90 - 1200 |% | Six channels on N06 /6xlrep | 85 - m0 |% With Ipep = 250 WA; Ry = 1,5 KS (+ 5%) | | | One channel on lot/lref 90 - i110 |% | Six channels on | l06/6xlrep | 85 = }105|% | Output current one channel on lot 225 | 275 | WA Output current six channels on log 13 F 16 |ma With resistor supplying rep (note 4) | Output current one channel on i to1 150 |- 360 [uA | Output current six channels on | lo6 og |= 19 |ma, Load resistance RL 600 | 5 |- a | D.C, leakage current all channels off -ILo - - 10 BA | Maximum current difference between | left and right current sinks (note ) + lomax = . 15 \% Signal-to-noise ratio (note 6) {S/N - [toe - [dB November 1986 419SAA1099 J L A.C. CHARACTERISTICS. Vpp = 5 V # 10%; Tamb = 0 to 70 °C; timing measurements taken at 2,0 V for a logic 1 and 0,8 V for a logic 0 unless otherwise specified (see waveforms Figs 3 and 4) —— parameter | symbol min, | typ. unit Bus interface timing (see Fig. 3) | AO set-up time to CS fall tasc 0 = - ns | | CS Low to WR fall tesw | 30 = = ns AO set-up time to WR fall | tasw | 50 - - | ns WR LOW time | we 100 | - - jms | Data bus valid to WR rise | tesw }wo j- |= prs | DTACK fall delay from WR fall (note 7) tDEW 0 - 85 ins | | AO hold time from WR HIGH tAHW 0 - ea ins | | CS hold time from WA HIGH | tcnw 0 = io ns | Data bus hold time from WR HIGH tDHW |o - [- ns | DTACK rise delay from WR HIGH | torw 0 = }100 [ns | Bus cycle time (note 8) tey aterk | - = | Bus cycle time (note 9) tey 18teLK | - - | j Clock input timing (see Fig. 4) | Clock period Htetk 120/125 | 255 | ns Clock LOW time tLow | 55 - - ns Clock HIGH time | tHicH | 55 - - ns | 1 __l J Notes to the characteristics 1. Using an external constant current generator to provide a nominal Iref or external resistor connected to Vp. 2. This output is short-circuit protected to Vpp and Vgs. 3. Measured with Iref a constant value between 100 and 400 yA; load resistance (R) allowed to match £12 (5%) in all applications via: Ri = 0.6 [lreg] “' —16 [Ipeg] °° = 12% 4. Measured with Rref = 10 k& (+ 5%) connected between Iref and Vpp: RL = 1,5 k& (+ 6%); OUTR and OUTL short-circuit protected to Vgg. 5, Left and right outputs must be driven with identical configuration. 6, Sample tested value only. 7. This timing parameter only applies when no wait states are required; otherwise parameter is invalid. 8. The minimum bus cycle time of four clock periods is for loading all registers except the amplitude 9. The minimum bus cycle time of 16 clock periods is for loading the amplitude registers. In a system using DTACK it is possible to achieve minimum times of 500 ns, Without DTACK the parameter given must be used. 420 November 1986Microprocessor controlled stereo sound generator SAA1099 for sound effects and music synthesis a ! tase) ry = tanw — po-07 DTACK Fig. 3. Bus interface waveforms. Je tig >} | |= tLow — | — teuxk————_r}rza7a12 Fig, 4 Clock input waveform. November 1986 421SAA1099 APPLICATION INFORMATION Device operation The SAA 1099 uses pulse width modulation to achieve amplitude and envelope levels. The twelve signals are mixed in an analogue format (6 ‘left’ and 6 ‘right’) before leaving the chip. The amplitude and envelope signals chop the output at @ minimum rate of 62,5 kHz, compared with the highest tone output of 7,81 kHz. Simple external low-pass filtering is used to remove the high frequency components. Rates quoted are based on the input of a 8 MHz clock, A data bus based write only structure is used to load the on-board registers. The data bus is used to load the address for a register, and subsequently the data to that register. Once the address is loaded multiple data loads to that register can be performed. The selection of address or data is made by the single address bit AO, as shown in register maps Table 1 and Table 2. ‘The bus control signals WA and C5 are designed to be compatible with a wide range of microprocessors, a DTACK output is included to optimise the interface with an S68000 series microprocessor. In most bus cycles DTACK will be returned immediately, this applies to all register address load cycles and all except amplitude data load cycles. With respect to amplitude data, a number of wait cycles may need to be performed, depending on the time since the previous amplitude load. DTACK will indicate the number of required waits. Register description (see Tables 2 and 3) The amplitudes are assigned with ‘left’ and ‘right’ components in the same byte, on a channel by channel basis. The spare locations that are left between blocks of registers is to allow for future expansion, and should be written as zero’s. The tone within an octave is defined by eight bits and the octave by three bits, Note that octaves are paired (0/1, 2/3 etc.). The frequency and noise enables are grouped together for ease of programming. The controls for noise ‘colour’ (clock rate) are grouped in one byte. The envelope registers are positioned in adjacent locations. There are two types of envelope controls, direct acting controls and buffered controls. The direct acting controls always take immediate effect, and are ‘* Envelope enable (reset) © Envelope resolution (16/8 level) The buffered controls are acted upon only at the times shown in Fig, 5 and control selection of: © Envelope clock source ‘© Waveform type © Inverted/non-inverted ‘right’ component Table 1 External memory map select data bus inputs AO | 07 DSP) D241 ROO | sscternseee o | 07 03 | 02 | 01 | 00,| data for internal registers 1 x 3 | A2 | Ai | AO\| internal register address Where X = don’t care state. 422 November 1986Microprocé controlled stereo sound generator SAA1099 for sound effects and music synthesis Table 2 Internal register map register data bus inputs address |D7_ [D6 |D5 |D4 |D3 |o2 |p1 |po | °Pustions 00 | aros|ano2| anor] arco] aLo3 | ALo2| ALO1 | ALOO | amplitude O right channel; | | eft channe! or 1 rit fa fa fa 1 [1 [amplitude 1 right/left 02 |2 2 2 2 (2 2 2 |2 amplitude 2 right/left o }3 (3 [3 |3 |3 |3 [3 [3 — |amplitude 3 right/left (oer peers | A ueeee | agrees 4) | 4 |4 4° |4 | amplitude 4 right/left | 05 [5 (5 [5 [5 [5 |5 |5 [5 _—_ J amplitude 6 right/teft oe |x |x |x |x jx |x |x Ix | oy |x [x |x jx |x |x [x Ix | 08 | F07 | FOB |FOS |FO4 |FO3 |FO2 | FOI | FOO | frequency of tone 0 | o9 ft it) fa 1 1 1 1 it frequency of tone 1 | oA |2 j2 |2 {2 2 |2 2 {2 frequency of tone 2 o 13/3 |3 3 (3 |3 {3 |3 | frequency of tone 3 oc ja ja | 4 [4 |4 (4 |4 |4_ | frequency of tone 4 op | F57 | F56 |F55 |F54 | FS3 | F52 | F51 | FSO | frequency of tone S oe |x [x x x |x x x x | oF |x |x |x |x |x 1x x x 10. |x [012 [011 jo10 |x 002 }o01 |000 |octave 1; octave 0 11) x [032 [031 ]030 |x |022 }021 | 020 | octave 3; octave 2 12 |X |052 [051 |os0 |x |042 |041 | 040 |octave 5; octave 4 3 )xX [x |x [x |x [x jx |x 14 [x x | FES | Fea FE3 | FE2 |FE1 | FEO | frequency enable 1s |x |x [nes [Nea [NES |NE2 |NE1 | NEO |noise enable | 16 |X |X INIT |NIO |X |X — | NOT | NOO | noise generator 1; | | | | noise generator 0 woix ix |x ix jx |x ix |x 18 | £07 |x | £05 |E04 |£03 |£02 £01 | £00 |envelope generator 0 19 £17 |X | £15 | E14 |£13 |e12 |E11 | £10 |envelope generator 1 wa ix [xX jx |x |x ix [x |x RK XX Hrequency reset (all channels) We |X |X |X |X |X |X RST | SE || sound enable (all channels) wo jx |x |x |x Ix |x |x [x we |x |x |x jx |x |x [x Ix i weefx [x fx |x |x [x |x |x | Where: All don’t cares (X) should be written as zero’s. 00 to 1F block of registers repeats eight times in the block between addresses 00 to FF (full internal memory map). November 1986 423SAA1099 APPLICATION INFORMATION (continued) Table 3. Register description bit description ARn3; ARN2; 4 bits for amplitude control ARn1; ARnO of right channel (n= 0,5) 0.0.00 minimum amplitude (off) | | 1.1.11. maximum amplitude ALn3;ALn2; | 4 bits for amplitude control Lat; ALnO of left channel (n=05) 0.0.00 minimum amplitude (off) 1111 maximum amplitude Fn7 to Fn0 | 8 bits for frequency control {n= 0,5) | of the six frequency generators | 00000000 Itowest frequency | 11111141 highest frequency On2;On1;On0 | 3 bits for octave control (n=0,5) 0.00 lowest octave (31 Hz to 61 Hz) | 001 (61 Hz to 122 Hz) o10 (122 Hz to 244 Hz) | 011 (245 Hz to 488 Hz) | / 100 (489 Hz to 977 Hz) | 101 (978 Hz to 1,95 kHz) 110 (1,96 kHz to 3,91 kHz) 111 highest octave (3,91 kHz to 7,81 kHz) | frequency enable bit (one tone per generator) FEn = 0 indicates that frequency ‘n’ is off noise enable bit (one tone per generator) NEn = 0 indicates that noise 'n’ is off Nn1; Nno (n= 0,1) 2 bits for noise generator control. These bits select the noise generator rate (noise ‘colour') Nn1 NnO clock frequency 0 0 31,3kHz 0 1 18,6 kHz 1 0 7,6 kHz 11 61 Hz to 15,6 kHz (frequency generator 0/3) 424 November 1986Microprocessor controlled stereo sound generator for sound effects and music synthesis SAA1099 bit description En?; En5 to End 7 bits for envelope control (n=0,1) End 0 left and right component have the same envelope 1 right component has inverse of envelope that is applied to left component En3. €n2 Ent 0 0 0 zero amplitude 0 0 71 — maximum amplitude 0 1 0 single decay 0 1° 1 repetitive decay | 1 0 0 Single triangular | 1 0 1 repetitive triangular | 4 1 0 single attack 1 1 1 repetitive attack End 0 4 bits for envelope control (maximum frequency = 977 Hz) 1 3bits for envelope control (maximum frequency = 1,95 kHz) | Ens 0 internal envelope clock (frequency generator 1 or 4) 1__ external envelope clock (address write pulse) En? i 0 reset (no envelope control} | 1 envelope control enabled SE SE sound enable for all channels | (reset on power-up to 0) | | 0 all-channels disabled | | 1 allchannels enabled RST Reset signal to all frequency generators 0 allgenerators enabled | 1 all generators reset and synchronized Note Alll rates given are based on the input of a 8 MHz clock. November 1986 425SAA1099 J L APPLICATION INFORMATION (continued) scwlope ertr nota alone generator sive ‘en = 01 (ent n3 Enz Ent Eno oo 0 0 ein} —_— x & + (2) oi. le itil t t a an “a === u (2) ot, 0 100 erie 1000 roto ity $ a Si 1100 a —— oy _ ‘ 7 See mere BaAM ALM ALA + ‘ + bet il is) 4) (4) tia eee YT, Ze Zanl nal Pr LD ein) of f th 7287813 Fig. 5 Envelope waveforms, 426 November 1986SAA1099 Microprocessor controlled stereo sound generator for sound effects and music synthesis Notes to Fig. 5 (1) The level at this time is under amplitude control only (En7 = (2) When the generator is active (En7 = 1) the maximum level possible is 7/8ths of the amplitude level. ; no envelope). (3) After position (3) the buffered controls will be acted upon when loaded, (4) At positions (4) the buffered controls will be acted upon if already loaded. (5) Waveforms ‘a to ‘h’ show the left channel (En0 = 0; left and right components have the samme envelope). Waveform ‘i’ shows the right channel (EnO = 1; right component inverse of envelope applied to left). rr AMPLIFI FILTERS, alia UK (ent) a ~ |__, tte channe | Ce HB eee * Jl Ir ft L od 1 Pees | vecooen Fig. 6 Typical application circuit diagram. November 1986 427