Byte Addressability Byte addressing refers to hardware architectures which support accessing individual bytes of data rather than only larger units called words, which would be word-addressable. Memory is a storage component in the Computer used to store application programs. The Memory Chip is divided into equal parts called as “CELLS”. Each Cell is uniquely identified by a binary number called as “ADDRESS”. For example, the Memory Chip configuration is represented as ’64 K x 8’ as shown in the figure below. MEMORY CHIP RI [TATION 64K X 8 This indicates the This indicates the size number of celis in of the Cell (the number the memory chip of bits that can be ie. 64K cells(here) stored in the Cell) ie. 8 bits(here) The following information can be obtained from the memory chip representation shown above: 1. Data Space in the Chip = 64K X 8 2. Data Space in the Cell = 8 bits 3. Address Space in the Chip = =16 bits Now we can clearly state the difference between Byte Addressable Memory & Word Addressable Memory. Word Addressable Memory Byte Addressable MemoryWhen the data space in the cell = 8 bits then the corresponding address space is called as Byte Address. Based on this data storage i.e, Bytewise storage, the memory chip configuration is named as Byte Addressable Memory. For eg. : 64K X 8 chip has 16 bit Address and cell size = 8 bits (1 Byte) which means that in this chip, data is stored byte by byte. Big-Endian and indian When the data space in the cell = word length of CPU then the corresponding address space is called as Word Address. Based on this data storage i.e. Wordwise storage, the memory chip configuration is named as Word Addressable Memory. For eg. : For a 16-bit CPU, 64K X 16 chip has 16 bit Address & cell size = 16 bits (Word Length of CPU) which means that in this chip, data is stored word by word, Big-endian is an order in which the "big end" (most significant value in the sequence) is stored first (at the lowest storage address). Little-endian is an order in which the "little end" (least significant value in the sequence) is stored first. For example, in a big-endian computer, the two bytes required for the hexadecimal number 4F52 would be stored as 4F52 in storage (if 4F is stored at storage address 1000, for example, 52 will be at address 1001). In a little-endian system, it would be stored as 4F52 (52 at address 1000, 4F at 1001). Word Alignment Data Structure alignment Data structure alignment is the way data is arranged and accessed in computer memory. Data alignment and Data structure padding are two different issues but are related to each other and together known as Data Structure alignment. Data alignment: Data alignment means putting the data in memory at address equal to some multiple of the word size. This increases the performance of system due to the way the CPU handles memory.Data Structure Padding: Now, to align the data, it may be necessary to insert some extra bytes between the end of the last data structure and the start of the next data structure as the data is placed in memory as multiples of fixed word size. This insertion of extra bytes of memory to align the data is called data structure padding. Consider the structure as shown below: struct t char a; short int b; int ¢; char d; 3 Now we may think that the processor will allocate memory to this structure as shown below: Size of 1 block = 1 byte Size of 1 row = 4 byte b b = a c c ey da The total memory allocated in this case is 8 bytes. But this never happens as the processor can access memory as fixed word size of 4 bytes. So, the integer variable c can not be allocated memory as shown above. An integer variable requires 4 bytes. The correct way of allocation of memory is shown below for this structure using padding bytes. Size of 1 block = 1 byte Size of 1 row = 4 byteThe processor will require a total of 12 bytes for the above structure to maintain the data alignment. Instructions and Instructions Sequencing INSTRUCTIONS & INSTRUCTION SEQUENCING The tasks carried out by a computer program consist of a sequence of small steps, such as adding two numbers, testing for a particular condition, reading a character from the keyboard, or sending a character to be displayed on a display screen. © A computer must have instructions capable of performing 4 types of operations: 1) Data transfers between the memory and the registers (MOV, PUSH, POP, XCHG). 2) Arithmetic and logic operations on data (ADD, SUB, MUL, DIV, AND, OR, NOT). 3) Program sequencing and control([Link], LOOP, INT). 4) 1/0 transfers (IN, OUT). Instruction Sequencing and Execution Execution of instruction is a two-step procedure. In the first step, the instruction is fetched from memory. In the second step, the instruction is executed. First Step-> Instruction Fetch The processor has a register named program counter which has the address of the instruction that has to be executed next. To start the execution of a program, the address of first instruction has to be placed in the program counter. After the address of first instruction is placed in the program counter, the processor uses this address to fetch the first instruction. As soon as the first instruction is fetched the content in program counter is incremented by the word length (the group of n bits that can store a single, basic instruction) i.e, now, it has the address of next successive instruction to be executed. After fetching the instruction from memory location it is placed in the instruction register of the processor. Second Step -> Instruction executionIn the second step, the processor examines the instruction present in the instruction register and find out which operation has to be performed. It first fetches the operands involved in the instruction from the memory or processor register. Then the processor performs the arithmetic and logical operation and stores the result in the destination location mention in the instruction During this time the content of program counter is incremented so that it could point next instruction for execution. This execution of instructions in increasing order of addresses is straight line sequencing. Subroutines:- In computers, a subroutine is a sequence of program instructions that perform a specific task, packaged as a unit. This unit can then be used in programs wherever that particular task have to be performed. A subroutine is often coded so that it can be started (called) several times and from several places during one execution of the program, including from other subroutines, and then branch back (return) to the next instruction after the call, once the subroutine's task is done. It is implemented by using Call and Return instructions. Instructions to implement Subroutines: “The 8085 microprocessor has two instructions to implement the subroutines. They are CALL and RET. The CALL instruction is used in the main program to call a subroutine and RET instruction is used at the end of the subroutine to return to the main program Whenever the instructions in a subroutine are required to be executed, we branch program control to the subroutine using th CALL instruction. Advantages of Subroutine — 1. Decomposing a complex programming task into simpler steps. 2. Reducing duplicate code within a program. 3. Enabling reuse of code across multiple programs 4. Improving tractability or makes debugging of a program easy.Program to Add Two 32 Bit Numbers Write a Program to Add Two 32 Bit Numbers in Assembly language . To add 32 bit numbers AX Register should load LSB of the number . BX Register should load MSB of the number of the first Number. We have two double word numbers i.e. 32 bit numbers. Initially we will load the first 32 bit into the registers AX and BX. AX contains the LSB while BX contains the MSB, using MOV instruction. Now we will load the second 32 bit number into the registers CX and DX with CX containing the LSB and DX containing the MSB. First we will add the two LSBs ie. contents of AX and CX registers, using ADD instruction. Now we will the contents of the two MSBs i.e. contents of BX and DX registers. For this addition we will use the ADC instruction (add with carry) so that if any carry is generated in the LSB addition it will be added. The result is stored in AX and BX registers. AX contains the LSB and BX contains the MSB after addition. Display the result using display routine. Algorithm to Add Two 32 Bit Numbers Step! —: Initialize the data segment. Step ll: Load the LSB of first number into AX register. Step ill: Load the MSB of first number into BX register. Step IV: Load the LSB of the second number into CX register. StepV —: Load the MSB of the second number into Dx register. Step VI: Add the LSBs of two number. Step VIl_ : Add the MSBs of two numbers along with carry. Step Vill : Display the result. StepIX : Stop. Hard Disk Drive (HDD) Secondary memory: Ahard disk is a memory storage device which looks like this:Used Sectors Platterd ‘Used Sectors Un-used Sector Cylinder showing Concept of Cylinder, Tracks and Sectors Track Sectar _~ Track Disk Seetor The disk is divided into tracks. Each track is further divided into sectors. Read-Write(R-W) head moves over the rotating hard disk. Itis this Read-Write head that performs all the read and write operations on the disk and hence, position of the R- W head is a major concern. To perform a read or write operation on a memory location, we need to place the R-W head over that position. Some important terms must be noted here:1. Seek time — Seek time is the time required to move the disk arm to the required track from it's current position. 2. Rotational latency — Rotational latency (sometimes called rotational delay or just latency) is the delay waiting for the rotation of the disk to bring the required disk sector under the read-write head. 3. Access Time — The access time or response time of a rotating drive is a measure of the time it takes before the drive can actually transfer data. The key components that are typically added together to obtain the access time are: Seek time Rotational Latency Command Processing time Settle time 4, Controller time - The processing time taken by the controller. 5. Data transfer time — Time taken to transfer the required amount of data. It depends upon the rotational speed. Example — Consider a hard disk with 4 surfaces 64 tracks/surface 128 sectors/track 256 bytes/sector 1, What is the capacity of the hard disk? Disk capacity = surfaces * tracks/surface * sectors/track * bytes/sector Disk capacity = 4 * 64 * 128 * 256 Disk capacity = 8 MB 8086 Microprocesso! 8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines that provides up to 1MB storage. It consists of powerful instruction set, which provides operations like multiplication and division easily. It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for system having a single processor.Features of 8086 The most prominent features of a 8086 microprocessor are as follows ~ Ithas an instruction queue, which is capable of storing six instruction bytes from the memory resulting in faster processing It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit extemal data bus resulting in faster processing. Itis available in 3 versions based on the frequency of operation - © 8086 — 5MHz © 8086-2 — 8MHz © (c)8086-1 — 10 MHz It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance. Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue. Execute stage executes these instructions. It has 256 vectored interrupts. It consists of 29,000 transistors. Comparison between 8085 & 8086 Microprocessor 8086 Size - 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor. Address Bus - 8085 has 16-bit address bus while 8086 has 20-bit address bus. Memory - 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory. Instruction - 8085 doesn't have an instruction queue, whereas 8086 has an instruction queue Pipelining - 8085 doesn't support a pipelined architecture while 8086 supports a pipelined architecture. WO - 8085 can address 28 = 256 I/O's, whereas 8086 can access 216 = 65,536 /O's. Cost - The cost of 8085 is low whereas that of 8086 is high. Microprocessor is divided into two functional units, i.e., EU (Execution Unit) and BIU (Bus Interface Unit). EU (Execution Unit)Execution unit gives instructions to BIU stating from where to fetch the data and then decode and execute those instructions. Its function is to control operations on data using the instruction decoder & ALU. EU has no direct connection with system buses as shown in the above figure, it performs operations over data through BIU: Let us now discuss the functional parts of 8086 microprocessors. ALU It handles all arithmetic and logical operations, like +, -, x, /, OR, AND, NOT operations. Flag Register Itis a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored in the accumulator. It has 9 flags and they are divided into 2 groups ~ Conditional Flags and Control Flags. Conditional Flags It represents the result of the last arithmetic or logical instruction executed, Following is the list of conditional flags ~ + Carry flag ~ This flag indicates an overflow condition for arithmetic operations. + Auxiliary flag- When an operation is performed at ALU, it results in a carry/barrow from lower nibble (i.e. D0 — D3) to upper nibble (i.e. D4 — D7), then this flag is set, ie. carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to BCD conversion. + Parity flag - This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits of the result contains even number of 1's, then the Parity Flag is set. For odd number of 1's, the Parity Flag is reset. + Zero flag - This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0. + Sign flag - This flag holds the sign of the result, i.e. when the result of the operation is negative, then the sign flag is set to 1 else set to 0. + Overflow flag - This flag represents the result when the system capacity is exceeded. Control Flags Control flags controls the operations of the execution unit. Following is the list of control flags —+ Trap flag - It is used for single step control and allows the user to execute one instruction at a time for debugging. If it is set, then the program can be run in a single step mode. + Interrupt flag - It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption of a program. It is set to 1 for interrupt enabled condition and set to 0 for interrupt disabled condition + Direction flag - It is used in string operation. As the name suggests when it is set then string bytes are accessed from the higher memory address to the lower memory address and vice-a-versa. General purpose register There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers can be used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. Its referred to the AX, BX, CX, and DX respectively. + AX register - It is also known as accumulator register. It is used to store operands for arithmetic operations. + BX register - It is used as a base register. It is used to store the starting base address of the memory area within the data segment. + CX register - It is referred to as counter. It is used in loop instruction to store the loop counter. + DX register - This register is used to hold /O port address for |/O instruction. Stack pointer register It is a 16-bit register, which holds the address from the start of the segment to the memory location, where a word was most recently stored on the stack. BIU (Bus Interface Unit) BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses, fetching instructions from the memory, reading data from the ports and the memory as well as writing data to the ports and the memory. EU has no direction connection with System Buses so this is possible with the BIU. EU and BIU are connected with the Internal Bus. It has the following functional parts - + Instruction queue - BIU contains the instruction queue. BIU gets upto 6 bytes of next instructions and stores them in the instruction queue. When EU executes instructions and is ready for its next instruction, then it simply reads the instruction from this instruction queue resulting in increased execution speed.+ Fetching the next instruction while the current instruction executes is called pipelining + Segment register - BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of instructions and data in memory, which are used by the processor to access memory locations. It also contains 1 pointer register IP, which holds the address of the next instruction to executed by the EU © CS- It stands for Code Segment. It is used for addressing a memory location in the code segment of the memory, where the executable program is stored © DS - It stands for Data Segment. It consists of data used by the program andis accessed in the data segment by an offset address or the content of other register that holds the offset address. © SS - It stands for Stack Segment. It handles memory to store data and addresses during execution. © ES - It stands for Extra Segment. ES is additional data segment, which is used by the string to hold the extra destination data. + Instruction pointer - It is a 16-bit register used to hold the address of the next instruction to be executed