Common Weakness Enumeration

A community-developed list of SW & HW weaknesses that can become vulnerabilities

CWE Glossary Definition

Description

The product uses physical debug or test interfaces with support for multiple access levels, but it assigns the wrong debug access level to an internal asset, providing unintended access to the asset from untrusted debug agents.

Extended Description

Debug authorization can have multiple levels of access, defined such that different system internal assets are accessible based on the current authorized debug level. Other than debugger authentication (e.g., using passwords or challenges), the authorization can also be based on the system state or boot stage. For example, full system debug access might only be allowed early in boot after a system reset to ensure that previous session data is not accessible to the authenticated debugger.

Common Consequences

This table specifies different individual consequences associated with the weakness. The Scope identifies the application security area that is violated, while the Impact describes the negative technical impact that arises if an adversary succeeds in exploiting this weakness. The Likelihood provides information about how likely the specific consequence is expected to be seen relative to the other consequences in the list. For example, there may be high likelihood that a weakness will be exploited to achieve a certain impact, but a low likelihood that it will be exploited to achieve a different impact.

Impact	Details
Read Memory	Scope: Confidentiality If a protection mechanism does not ensure that internal assets have the correct debug access level during each boot stage or change in system state, an attacker could obtain sensitive information from the internal asset using a debugger.
Modify Memory	Scope: Integrity
Gain Privileges or Assume Identity; Bypass Protection Mechanism	Scope: Authorization, Access Control

Potential Mitigations

Phase(s)	Mitigation
Architecture and Design; Implementation	For security-sensitive assets accessible over debug/test interfaces, only allow trusted agents. Effectiveness: High
Architecture and Design	Apply blinding [REF-1219] or masking techniques in strategic areas. Effectiveness: Limited
Implementation	Add shielding or tamper-resistant protections to the device, which increases the difficulty and cost for accessing debug/test interfaces. Effectiveness: Limited

Relationships

This table shows the weaknesses and high level categories that are related to this weakness. These relationships are defined as ChildOf, ParentOf, MemberOf and give insight to similar items that may exist at higher and lower levels of abstraction. In addition, relationships such as PeerOf and CanAlsoBe are defined to show similar weaknesses that the user may want to explore.

Relevant to the view "Research Concepts" (View-1000)

Nature	Type	ID	Name
ChildOf	Class - a weakness that is described in a very abstract fashion, typically independent of any specific language or technology. More specific than a Pillar Weakness, but more general than a Base Weakness. Class level weaknesses typically describe issues in terms of 1 or 2 of the following dimensions: behavior, property, and resource.	863	Incorrect Authorization

Relevant to the view "Hardware Design" (View-1194)

Nature	Type	ID	Name
MemberOf	Category - a CWE entry that contains a set of other entries that share a common characteristic.	1207	Debug and Test Problems

Modes Of Introduction

The different Modes of Introduction provide information about how and when this weakness may be introduced. The Phase identifies a point in the life cycle at which introduction may occur, while the Note provides a typical scenario related to introduction during the given phase.

Phase	Note
Architecture and Design
Implementation

Applicable Platforms

This listing shows possible areas for which the given weakness could appear. These may be for specific named Languages, Operating Systems, Architectures, Paradigms, Technologies, or a class of such platforms. The platform is listed along with how frequently the given weakness appears for that instance.

Demonstrative Examples

Example 1

The JTAG interface is used to perform debugging and provide CPU core access for developers. JTAG-access protection is implemented as part of the JTAG_SHIELD bit in the hw_digctl_ctrl register. This register has no default value at power up and is set only after the system boots from ROM and control is transferred to the user software.

(bad code)

Example Language: Other 

This means that since the end user has access to JTAG at system reset and during ROM code execution before control is transferred to user software, a JTAG user can modify the boot flow and subsequently disclose all CPU information, including data-encryption keys.

Example 2

The example code below is taken from the CVA6 processor core of the HACK@DAC'21 buggy OpenPiton SoC. Debug access allows users to access internal hardware registers that are otherwise not exposed for user access or restricted access through access control protocols. Hence, requests to enter debug mode are checked and authorized only if the processor has sufficient privileges. In addition, debug accesses are also locked behind password checkers. Thus, the processor enters debug mode only when the privilege level requirement is met, and the correct debug password is provided.

The following code [REF-1377] illustrates an instance of a vulnerable implementation of debug mode. The core correctly checks if the debug requests have sufficient privileges and enables the debug_mode_d and debug_mode_q signals. It also correctly checks for debug password and enables umode_i signal.

However, it grants debug access and changes the privilege level, priv_lvl_o, even when one of the two checks is satisfied and the other is not. Because of this, debug access can be granted by simply requesting with sufficient privileges (i.e., debug_mode_q is enabled) and failing the password check (i.e., umode_i is disabled). This allows an attacker to bypass the debug password checking and gain debug access to the core, compromising the security of the processor.

A fix to this issue is to only change the privilege level of the processor when both checks are satisfied, i.e., the request has enough privileges (i.e., debug_mode_q is enabled) and the password checking is successful (i.e., umode_i is enabled) [REF-1378].

Selected Observed Examples

Note: this is a curated list of examples for users to understand the variety of ways in which this weakness can be introduced. It is not a complete list of all CVEs that are related to this CWE entry.

Reference	Description
CVE-2019-18827	After ROM code execution, JTAG access is disabled. But before the ROM code is executed, JTAG access is possible, allowing a user full system access. This allows a user to modify the boot flow and successfully bypass the secure-boot process.

Weakness Ordinalities

Ordinality	Description
Primary	(where the weakness exists independent of other weaknesses)

Detection Methods

Method	Details
Manual Analysis	Check 2 devices for their passcode to authenticate access to JTAG/debugging ports. If the passcodes are missing or the same, update the design to fix and retest. Check communications over JTAG/debugging ports for encryption. If the communications are not encrypted, fix the design and retest. Effectiveness: Moderate

Memberships

This MemberOf Relationships table shows additional CWE Categories and Views that reference this weakness as a member. This information is often useful in understanding where a weakness fits within the context of external information sources.

Nature	Type	ID	Name
MemberOf	View - a subset of CWE entries that provides a way of examining CWE content. The two main view structures are Slices (flat lists) and Graphs (containing relationships between entries).	1343	Weaknesses in the 2021 CWE Most Important Hardware Weaknesses List
MemberOf	Category - a CWE entry that contains a set of other entries that share a common characteristic.	1396	Comprehensive Categorization: Access Control
MemberOf	Category - a CWE entry that contains a set of other entries that share a common characteristic.	1433	2025 MIHW Supplement: Expert Insights

Vulnerability Mapping Notes

Usage	ALLOWED (this CWE ID may be used to map to real-world vulnerabilities)
Reason	Acceptable-Use
Rationale	This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.
Comments	Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Notes

Relationship

CWE-1191 and CWE-1244 both involve physical debug access, but the weaknesses are different. CWE-1191 is effectively about missing authorization for a debug interface, i.e. JTAG. CWE-1244 is about providing internal assets with the wrong debug access level, exposing the asset to untrusted debug agents.

Related Attack Patterns

CAPEC-ID	Attack Pattern Name
CAPEC-114	Authentication Abuse

References

[REF-1056]	F-Secure Labs. "Multiple Vulnerabilities in Barco Clickshare: JTAG access is not permanently disabled". <https://labs.withsecure.com/advisories/multiple-vulnerabilities-in-barco-clickshare>. (URL validated: 2025-08-04)
[REF-1057]	Kurt Rosenfeld and Ramesh Karri. "Attacks and Defenses for JTAG". <https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5406671>.
[REF-1219]	Monodeep Kar, Arvind Singh, Santosh Ghosh, Sanu Mathew, Anand Rajan, Vivek De, Raheem Beyah and Saibal Mukhopadhyay. "Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator". 2018-02. <https://arxiv.org/pdf/1802.09096>. (URL validated: 2025-08-04)
[REF-1377]	"csr_regile.sv line 938". 2021. <https://github.com/HACK-EVENT/hackatdac19/blob/57e7b2109c1ea2451914878df2e6ca740c2dcf34/src/csr_regfile.sv#L938>. (URL validated: 2023-12-13)
[REF-1378]	"Fix for csr_regfile.sv line 938". 2021. <https://github.com/HACK-EVENT/hackatdac19/blob/a7b61209e56c48eec585eeedea8413997ec71e4a/src/csr_regfile.sv#L938C31-L938C56>. (URL validated: 2023-12-13)

Content History

Submissions
Submission Date	Submitter	Organization
2020-02-12 (CWE 4.0, 2020-02-24)	Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi	Intel Corporation
Contributions
Contribution Date	Contributor	Organization
2023-11-07	Chen Chen, Rahul Kande, Jeyavijayan Rajendran	Texas A&M University
	suggested demonstrative example
2023-11-07	Shaza Zeitouni, Mohamadreza Rostami, Ahmad-Reza Sadeghi	Technical University of Darmstadt
	suggested demonstrative example
2021-10-22	Hareesh Khattri	Intel Corporation
	clarified differences between CWE-1191 and CWE-1244, and suggested rephrasing of descriptions and names.
Modifications
Modification Date	Modifier	Organization
2025-12-11 (CWE 4.19, 2025-12-11)	CWE Content Team	MITRE
	updated Common_Consequences, Description
2025-09-09 (CWE 4.18, 2025-09-09)	CWE Content Team	MITRE
	updated References, Relationships
2024-02-29 (CWE 4.14, 2024-02-29)	CWE Content Team	MITRE
	updated Demonstrative_Examples, References
2023-06-29 (CWE 4.12, 2023-06-29)	CWE Content Team	MITRE
	updated Mapping_Notes
2023-04-27 (CWE 4.11, 2023-04-27)	CWE Content Team	MITRE
	updated References, Relationships
2022-04-28 (CWE 4.7, 2022-04-28)	CWE Content Team	MITRE
	updated Related_Attack_Patterns
2021-10-28 (CWE 4.6, 2021-10-28)	CWE Content Team	MITRE
	updated Demonstrative_Examples, Description, Detection_Factors, Maintenance_Notes, Name, Observed_Examples, Potential_Mitigations, References, Relationship_Notes, Relationships, Weakness_Ordinalities
2021-03-15 (CWE 4.4, 2021-03-15)	CWE Content Team	MITRE
	updated Maintenance_Notes
2020-08-20 (CWE 4.2, 2020-08-20)	CWE Content Team	MITRE
	updated Demonstrative_Examples, Name, Observed_Examples, Related_Attack_Patterns
Previous Entry Names
Change Date	Previous Entry Name
2021-10-28	Improper Access to Sensitive Information Using Debug and Test Interfaces
2020-08-20	Improper Authorization on Physical Debug and Test Interfaces

Page Last Updated: April 30, 2026

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